l6712a STMicroelectronics, l6712a Datasheet - Page 23

• Manufacturer Part Number: l6712a
• Description: Two-phase Interleaved Dc/dc Controller
• Manufacturer: STMicroelectronics

causes of instabilities are introduced jeopardizing good system behavior. One important consequence is
that the switching losses for the high side mosfet are significantly increased.
For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and
the GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance
(see Fig 16). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be
connected directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS
mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if imple-
mented) or in the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also
PGND when no power ground plane is implemented) must also be designed to handle current peaks in
excess of 2A (30 mils wide is suggested).
Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the sys-
tem efficiency.
The placement of other components is also important:
Figure 16. Device orientation (left) and sense nets routing (right).
I
Remote Amplifier: Place the external resistors near the device to minimize noise injection and refer to
SGND. The connections for these resistors (from the remote load) must be routed as parallel nets in order
to compensate losses along the output power traces and also to avoid the pick-up of any noise. Connect-
ing these pins in points far from the load will cause a non-optimum load regulation, increasing output tol-
erance.
Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins
in order to limit the noise injection into the device. The PCB traces connecting these resistors to the read-
– The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to min-
– Decoupling capacitor from VCC and SGND placed as close as possible to the involved pins.
– Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capac-
– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and
– Connect SGND to PGND plane on a single point to improve noise immunity. Connect at the load side
– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in re-
– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be ob-
Sense Connections.
imize the loop that is created.
itor sustains the peak currents requested by the low-side mosfet drivers.
Remote Amplifier Divider.
(output capacitor) if Remote Sense is not implemented to avoid undesirable load regulation effect.
ducing noise.
served on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin,
the device can absorb energy and it can cause damages. The voltage spikes must be limited by prop-
er layout, the use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber
network on the low side mosfets, to a value lower than 26V, for 20ns, at F
Towards HS mosfet
Towards HS mosfet
Towards LS mosfet
(30 mils wide)
(30 mils wide)
(30 mils wide)
To regulated output
To LS mosfet
To LS mosfet
(or sense resistor)
(or sense resistor)
SW
of 600kHz max.
ST L6917
L6712A L6712
23/27