x80201 Intersil Corporation, x80201 Datasheet
x80201
Related parts for x80201
x80201 Summary of contents
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... SCL 10 READY 11 1 X80200, X80201, X80202, X80203, X80204 January 21, 2005 Features • Sequence three voltage supplies independently - Core and Logic I/O VCC power sequencer for processor supplies - Power up and power down control - Voltage monitors have undervoltage lockout - Internal charge pump drives external N-channel FET ...
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... X80200, X80201, X80202, X80203, X80204 Functional Diagram VDDH 18 UVLO H 19 VDDM UVLO M VDDL 20 UVLO SETV 1 REF GND Pin Descriptions PIN NAME 1 SETV Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL. If unused connect to ground. ...
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... X80200, X80201, X80202, X80203, X80204 Absolute Maximum Ratings Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on given pin (Power Sequencing Functions): All V pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V DD CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... X80200, X80201, X80202, X80203, X80204 Power Sequencing Control Circuits SYMBOL PARAMETER V GATE_H, GATE_M GATE_ON GATE_L GATE_H, GATE_M GATE_L V Gate Voltage Drive (OFF) for GATE_H, GATE_OFF GATE_M, GATE_L I Gate Current Drive (ON) for GATE_H, GATE_ON GATE_M, GATE_L I Gate Sinking Current Drive (OFF) for ...
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... X80200, X80201, X80202, X80203, X80204 Serial bus Interface Electrical Characteristics SYMBOL PARAMETER V Signal Input Low Voltage IL V Signal Input High Voltage IH V Signal Output Low Voltage OL C Capacitive Load per bus segment BUS Capacitance SYMBOL PARAMETER C Output Capacitance (SDA) OUT C Input Capacitance (SCL) ...
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... X80200, X80201, X80202, X80203, X80204 Bus Interface AC Timing SYMBOL PARAMETER f Clock Frequency SCL t Clock Cycle Time CYC t Clock High Time HIGH t Clock Low Time LOW t Start Set-up Time SU:STA t Start Hold Time HD:STA t Stop Set-up Time SU:STO t SDA Data Input Set-up Time ...
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... X80200, X80201, X80202, X80203, X80204 Principles of Operation Power Sequencing Control (PSC) The Intersil X80200 supports a variety of sequencing applications. The sequencing can be voltage-based or time- based. Some examples are shown in Figure , Figure , and Figure in the Applications section. The X80200 allows for designs that can control the power sequencing three voltage supplies ...
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... X80200, X80201, X80202, X80203, X80204 The READY output pin reflects the condition of the VDDH input. READY is LOW as long as VDDH is below UVLO and remains LOW for a period of t PURST crosses UVLO , see Figure 4. Once VDDH rises above H UVLO and remains stable for t ...
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... X80200, X80201, X80202, X80203, X80204 SETV t GATE_L DELAY_DOWN REF FET “L” REF DRAIN (VFB) GATE_M FIGURE 5. VOLTAGE BASED SEQUENCING OF GATE_M AND GATE_L Power Supply Failure Conditions Should there be a power failure of VDDH, GATE_H, GATE_M and GATE_L charge pumps are all turned OFF when VDDH falls below the UVLO threshold ...
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... X80200, X80201, X80202, X80203, X80204 Register Information The Register Block is organized as follows: • Status Register (SR) (1 Byte). Located at address 00h. • Remote Shut Down Register (RSR) (1 Byte). Located at address FFh. Status Register (Volatile STAT_ STAT_ GATEH ...
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... X80200, X80201, X80202, X80203, X80204 SERIAL CLOCK AND DATA Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. (See Figure 7 ...
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... X80200, X80201, X80202, X80203, X80204 Read Operation A Read operation is initiated in the same manner as a write operation with the exception that the R/W bit of the Slave Address Byte is set to one. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. ...
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... X80200, X80201, X80202, X80203, X80204 SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE S S SIGNALS FROM SIGNALS FROM T T DEVICE DEVICE THE MASTER THE MASTER SDA BUS SDA BUS SIGNALS FROM SIGNALS FROM THE SLAVE ...
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... X80200, X80201, X80202, X80203, X80204 DC-DC PRIMARY #1 I/O VOLTAGES DC-DC #2 PGOOD1 DC-DC #3 OPTIONAL DELAY SMBus FIGURE 14. TELECOM BACKPLACE/SYSTEM POWER SUPPLY TIME BASED POWER SEQUENCING 14 H (OPTIONAL) CORE VOLTAGES PGOOD2 VFB VDDH GATE_H VDDM GATE_M REF GATE_L SETV ENS VDDL A0 PULL UP TO SET GATEH_EN ADDRESS HIGH ...
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... X80200, X80201, X80202, X80203, X80204 PRIMARY DC- I/O DC-DC #2 PGOOD1 7,8,55-57 V ID4:ID0 VRM 10 PWRGD POWER SUPPLY VCORE 53 OUTEN 5 SCL SDA 9 OPTION DELAY SMBus FIGURE 15. POWER SEQUENCING OF VRM SUPPLIES 15 POWER SEQUENCING (TIME BASED MODE) USING POWER GOOD SIGNALS X80200 VFB VDDH GATE_H VDDM GATE_M NC REF ...
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... X80200, X80201, X80202, X80203, X80204 Packaging Information All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...