lm9617 National Semiconductor Corporation, lm9617 Datasheet - Page 21

• Manufacturer Part Number: lm9617
• Description: Monochrome Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Functional Description
,
By default the pixel clock is a free running active low (pixel data
changes on the positive edge of the clock) with a period equal to
the internal hclk. The active edge of the clock can be pro-
grammed such that pixel data changes on the positive or nega-
tive edge of the clock.
14.3
The horizontal synchronisation output pin, hsync, is used as an
indicator for row data. The hsync output pin can be programmed
to operate in two modes as follows:
• Level mode should be used when the pixel clock, pclk, is pro-
• Pulse mode should be used when the pixel clock, pclk, is pro-
By default the first pixel data at the beginning of each row is
placed on the digital video bus as soon as hsync is activated. It
is possible to program up to 15 dummy pixels to be readout at
the beginning of each row before the real pixel data is readout.
This feature is supported for both level and pulse mode.
Confidential
pclk
d[11:0]
hsync
pclk
d[11:0]
grammed to operate in free running mode. In level mode the
hsync output pin will go to the specified level (high or low) at
the start of each row and remain at that level until the last
pixel of that row is read out on d[11:0] as shown in Figure 37.
The hsync level is always synchronized to the active edge of
pclk.
grammed to operate in data ready mode. In pulse mode the
hsync output pin will produce a pulse at the end of each row.
The width of the pulse will be a minimum of four pclk cycles
and its polarity can be programmed as shown in Figure 38.
The hsync level is always synchronized to the active edge of
pclk
hsync
invalid pixel data
invalid pixel data
invalid pixel data
a) hsync programmed to be active high (default)
Horizontal Synchronisation Output Pin (hsync)
pclk
d[11:0]
hsync
pclk
d[11:0]
b) hsync programmed to be active low
hsync
pclk
d[11:0]
pclk
d[11:0]
Row n
Figure 36. pclk in Data Ready Mode
Row n
Figure 38. hsync in Pulse Mode
Figure 37. hsync in Level Mode
a) hsync programmed to be active high
b) hsync programmed to be active low
a) pclk active edge negative
b) pclk active edge positive
Row n
Row n
(continued)
Row n+1
Row n+1
Row n+1
Row n+1
21
14.4
The vertical synchronisation output pin, vsync, is used as an
indicator for pixel data within a frame. The vsync output pin can
be programmed to operate in two modes as follows:
• Level mode should be used when the pixel clock, pclk, is pro-
• Pulse mode should be used when the pixel clock, pclk, is pro-
14.5
In odd/even mode the vsync signal is used to indicate when
pixel data from an odd and even field is being placed on the dig-
ital video bus d[11:0]. The polarity of vsync can still be pro-
grammed in this mode as shown in Figure 41
pclk
d[11:0]
vsync
pclk
d[11:0]
grammed to operate in free running mode. In level mode the
vsync output pin will go to the specified level (high or low) at
the start of each frame and remain at that level until the last
pixel of that row in the frame is placed on d[11:0] as shown in
Figure 39. The hsync level is always synchronized to the
active edge of pclk.
grammed to operate in data ready mode. In pulse mode the
vsync output pin will produce a pulse at the end of each
frame. The width of the pulse will be a minimum of four hclk
cycles and its polarity can be programmed as shown in Figure
40. The vsync level is always synchronized to the active edge
of pclk.
vsync
invalid pixel data
invalid pixel data
invalid pixel data
a) vsync programmed to be active high (default)
Vertical/Horizontal Synchronisation Pin (vsync)
Odd/Even Mode
pclk
d[11:0]
b) vsync programmed to be active low (default)
vsync
vsync
pclk
d[11:0]
b) vsync programmed to be active low
pclk
d[11:0]
vsync
vsync
a) vsync programmed to be active high
pclk
d[11:0]
Frame n
Frame n
Figure 41. vsync in odd/even Mode
b) vsync programmed to be active low
Figure 39. vsync in Level Mode
Figure 40. vsync in pulse mode
a) vsync programmed to be active high
Frame n
Odd Field
Odd Field
Frame n
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Frame n+1
Frame n+1
Even Field
Even Field
Frame n+1
Frame n+1