emc166sp16k Emlsi Inc., emc166sp16k Datasheet - Page 24
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emc166sp16k
Manufacturer Part Number
emc166sp16k
Description
1mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
1.EMC166SP16K.pdf
(65 pages)
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The
reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus.
The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength
should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured
at half-drive strength during testing. See Table 4 for additional information.
Table 4: Drive Strength
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to
valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous
READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to
the de-asserted or asserted state, respectively. When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going
valid or invalid. (See Figure 17.)
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT
signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
Figure 17: WAIT Configuration During Burst Operation
Note: Non-default BCR setting: WAIT active LOW.
BCR[5]
DQ[15:0]
0
0
1
1
WAIT
WAIT
CLK
BCR[4]
0
1
0
1
Drive Strength
(default)
D0
Full
1/2
1/4
D1
Impedance Typ (Ω )
D2
24
Reserved
25~30
100
50
End of row
D3
Use Recommendation
Don’t Care
104 MHz at light load
CL = 15pF or lower
CL = 30pF to 50pF
CL = 15pF to 30pF
EMC166SP16K
1Mx16 CellularRAM
BCR[8] = 0
BCR[8] = 1
Data valid in current cycle
Data valid in next cycle