tc94a48fg TOSHIBA Semiconductor CORPORATION, tc94a48fg Datasheet - Page 23

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tc94a48fg

Manufacturer Part Number
tc94a48fg
Description
Single-chip Audio Digital Signal Processor Single-chip Audio Digital Signal Processor
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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When the host microcontroller reads data from the TC94A48FG during the execution of a program, it
sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of
words to be read. Then, it transfers the 24-bit command, waits about 1fs, and then transfers an I2C
address of 31h, followed by a start condition. Finally, it reads a required number of 24-bit data words.
During a read, the host microcontroller should set the ACK bits to low but the ACK bit accompanying
the last eight bits of data must be high, thus causing the TC94A48FG to relinquish the SDA bus line
so that the host microcontroller can transmit a stop condition.
The host microcontroller should wait about 1fs after transferring a command because it has to wait
until the data to be read is set in the data buffer of the TC94A48FG.
Figure 16 shows the 24-bit data read procedure.
Reading 24-bit data
Transfer I2C
Transfer I2C
Transfer 24-bit command
START Condition
START Condition
Read 24-bit data (2)
Read 24-bit data (1)
STOP Condition
(data read = xxxx1xh)
Check ACK bit = “L”
Check ACK bit = “L”
Read 24-bit data (n)
Data read finished
Wait about 1fs
Figure 16 shows the 24-bit Data Read Procedure
Address
Address
(30h)
(31h)
23
Set a 16-bit address and the number
Can read up to eight 24-bit
If ACK = “H” , restart from
If ACK = “H” , restart from
of words to be transferred.
START condition.
START condition.
Set the last ACK bit to “H”
data words
TC94A48FG
2005-09-28

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