tc9444f TOSHIBA Semiconductor CORPORATION, tc9444f Datasheet - Page 11

• Manufacturer Part Number: tc9444f
• Description: Single-chip Karaoke Ic Ii
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.2
3.3
3.4
BOOT Command
interface settings.
required.
attenuator.
constant selection bit set by the ATTA command. After the soft mute is released, the digital
attenuator is restored to the set level.
= “H” clears data RAM. Therefore, the number of fs cycles required to completely clear data RAM
depends on the program. Normally, several cycles are required.
write operations (INIT operation).
RAM, take the following steps. First set the MUTE bit. Then, after waiting only the length of the
digital attenuator time constant, set RAMCLR to “H” to clear the data in RAM. Then set the
RAMCLR and MUTE bits to “L”. This will enable you to change the signal processing content without
any switching noise.
shift.
processing completely stops. Using the 20H command to turn key control off disables the use of
internal delay RAM in the key control processing, thus allowing delay RAM to be allocated to other
processing.
and to monaural key control. The key shift is set in semitone steps.
a value other than 0, the signal is intermittent. The soft mute automatically comes on to avoid
switching noise at this time. After the command is issued, the following steps are performed
automatically.
MUTE Command
KEYCON Command
One-byte command to initialize coefficient RAM.
Initializes coefficient RAM values to the internal BOOT ROM values, retaining the other command
After the BOOT command is received, initialization completes in a -fs cycle. Boot release is not
When reset is made by setting the RESET pin to “L”, boot is still executed.
One-byte command to clear data RAM and delay RAM, and to execute a soft mute using the digital
At a soft mute, the time constant is determined by the operation sampling frequency and the time
In data RAM, sequentially writing all-zero data (fixing the input data to 000000H) while RAMCLR
For a program which is written to in one place only, a 28-word update takes no more than 3 ms.
In delay RAM, after RAMCLR = H, 0000H is sequentially written to delay RAM at subsequent
When using delay RAM to significantly change the effect of the SFC processing, to clear the data in
One-byte command to control the amount of key shift. The CL value indicates the amount of key
The difference between the 20H command and the 28H command is the point at which key control
The amount of key shift set by the KEYCON command applies to both L and R stereo key control
As delay RAM is used in key control processing, when switching the key shift setting between 0 and
This series of processing operations takes around 46 ms to execute.
Mute ® Internal settings switched ® Mute released
Note 5: At a reset, the initial value is CL = 0H.
CH
1
MUTE: MUTE = “H” sets soft mute.
RAMCLR: RAMCLR = “H” clears data RAM and delay RAM.
Table 3.2 MUTE Command
3
0
11
2
0
CL
RAMCLR
1
MUTE
0
2002-01-11
TC9444F