attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 29

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

Minimizing Power
Consumption
Analog to Digital Converter
Analog Comparator
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
2535G–AVR–01/07
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possi-
ble, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog to Digital Con-
verter” on page 80 for details on ADC operation.
When entering Idle mode, the Analog Comparator should be disabled if not used. When
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-
erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 77 for details on how to configure the Analog Comparator.
If the Brown-out Detector is not needed in the application, this module should be turned
off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in
all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Brown-out Detec-
tion” on page 33 for details on how to configure the Brown-out Detector.
The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-
tion, the Analog Comparator or the ADC. If these modules are disabled as described in
the sections above, the internal voltage reference will be disabled and it will not be con-
suming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be
used immediately. Refer to “Internal Voltage Reference” on page 35 for details on the
start-up time.
If the Watchdog Timer is not needed in the application, this module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Interrupts” on page 42 for details on how to con-
figure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important thing is then to ensure that no pins drive resistive loads. In sleep
modes where both the I/O clock (clk
input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section “Digital Input
Enable and Sleep Modes” on page 47 for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or has an analog signal level close to
V
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to V
mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-
ter (DIDR0). Refer to “Digital Input Disable Register 0 – DIDR0” on page 79 for details.
CC
/2, the input buffer will use excessive power.
CC
/2 on an input pin can cause significant current even in active
I/O
) and the ADC clock (clk
ADC
) are stopped, the
29