pic24hj16gp304 Microchip Technology Inc., pic24hj16gp304 Datasheet - Page 37

• Manufacturer Part Number: pic24hj16gp304
• Description: High-performance, 16-bit Microcontrollers
• Manufacturer: Microchip Technology Inc.

TABLE 3-22:
3.3.3
Move instructions provide a greater degree of address-
ing flexibility than the other instructions. In addition to
the Addressing modes supported by most MCU
instructions, MOV instructions also support Register
Indirect with Register Offset Addressing mode. This is
also referred to as Register Indexed mode.
© 2007 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset
(Register Indexed)
Register Indirect with Literal Offset
Note:
Addressing Mode
MOVE (MOV) INSTRUCTION
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and the destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
PIC24HJ32GP202/204 and PIC24HJ16GP304
FUNDAMENTAL ADDRESSING MODES SUPPORTED
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA.)
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
The sum of Wn and Wb forms the EA.
The sum of Wn and a literal forms the EA.
Preliminary
In summary, move instructions support the following
addressing modes:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
3.3.4
Besides the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
Note:
Description
Not all instructions support all the address-
ing modes given above. Individual instruc-
tions may support different subsets of
these addressing modes.
OTHER INSTRUCTIONS
DS70289A-page 35