atmega161-4pi ATMEL Corporation, atmega161-4pi Datasheet - Page 74

• Manufacturer Part Number: atmega161-4pi
• Description: 8-bit Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

UART1 Control and Status
Registers – UCSR1A
74
ATmega161(L)
• Bit 7
This bit is set (one) when a received character is transferred from the Receiver Shift
Register to UDRn. The bit is set regardless of any detected framing errors. When the
RXCIEn bit in UCSRnB is set, the UART Receive Complete interrupt will be executed
when RXCn is set (one). RXCn is cleared by reading UDRn. When interrupt-driven data
reception is used, the UART Receive Complete Interrupt routine must read UDRn in
order to clear RXCn; otherwise, a new interrupt will occur once the interrupt routine
terminates.
• Bit 6
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift Register has been shifted out and no new data has been written to UDRn. This
Flag is especially useful in half-duplex communications interfaces, where a transmitting
application must enter Receive mode and free the communications bus immediately
after completing the transmission.
When the TXCIEn bit in UCSRnB is set, setting of TXCn causes the UART Transmit
Complete interrupt to be executed. TXCn is cleared by hardware when executing the
corresponding Interrupt Handling Vector. Alternatively, the TXCn bit is cleared (zero) by
writing a logical “1” to the bit.
• Bit 5
This bit is set (one) when a character written to UDRn is transferred to the Transmit Shift
Register. Setting of this bit indicates that the Transmitter is ready to receive a new char-
acter for transmission.
When the UDRIEn bit in UCSRnB is set, the UART Transmit Complete interrupt will be
executed as long as UDREn is set and the global interrupt enable bit in SREG is set.
UDREn is cleared by writing UDRn. When interrupt-driven data transmittal is used, the
UART Data Register Empty Interrupt routine must write UDRn in order to clear UDREn,
otherwise a new interrupt will occur once the interrupt routine terminates.
UDREn is set (one) during reset to indicate that the Transmitter is ready.
• Bit 4
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-
ing character is zero.
The FEn bit is cleared when the stop bit of received data is one.
• Bit 3
This bit is set if an Overrun condition is detected, i.e., when a character already present
in the UDRn Register is not read before the next character has been shifted into the
Receiver Shift Register. The ORn bit is buffered, which means that it will be set once the
valid data still in UDRn is read.
The ORn bit is cleared (zero) when data is received and transferred to UDRn.
Bit
$02 ($22)
Read/Write
Initial Value
–
–
–
–
–
RXC0/RXC1: UART Receive Complete
TXC0/TXC1: UART Transmit Complete
UDRE0/UDRE1: UART Data Register Empty
FE0/FE1: Framing Error
OR0/OR1: OverRun
RXC1
R
7
0
TXC1
R/W
6
0
UDRE1
R
5
1
FE1
R
4
0
OR1
R
3
0
R
2
–
0
U2X1
R/W
1
0
MPCM1
R/W
0
0
1228D–AVR–02/07
UCSR1A