at91m42800 ATMEL Corporation, at91m42800 Datasheet - Page 13

• Manufacturer Part Number: at91m42800
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

External Bus Interface
The External Bus Interface handles the accesses between
addresses 0x0040 0000 and 0xFFC0 0000. It generates
the signals that control access to the external devices, and
can be configured from eight 1-Mbyte banks up to four 16-
Mbyte banks. In all cases it supports byte, half-word and
word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the
The External Bus Interface features also the Early Read
Protocol, configurable for all the devices, that significantly
reduces access time requirements on an external device.
Peripherals
The AT91M42800 peripherals are connected to the 32-bit
wide Advanced Peripheral Bus. Peripheral registers are
only word accessible. Byte and half-word accesses are not
supported. If a byte or a half-word access is attempted, the
memory controller automatically masks the lowest address
bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated
(the AIC only has a 4-Kbyte address space).
Peripheral Registers
The following registers are common to all peripherals:
• Control Register – Write-only register that triggers a
• Mode Register – read/write register that defines the
• Data Registers – read and/or write register that enables
finished to prevent any bus contention in case the device
is too long in releasing the bus)
EBI to control one 16-bit device (Byte Access Select
mode) or two 8-bit devices in parallel that emulate a
16-bit memory (Byte Write Access mode).
command when a one is written to the corresponding
position at the appropriate address. Writing a zero has
no effect.
configuration of the peripheral. Usually has a value of
0x0 after a reset.
the exchange of data between the processor and the
peripheral.
• Status Register – Read-only register that returns the
• Enable/Disable/Status Registers – shadow command
Unused bits in the peripheral registers are shown as “–”
and must be written at 0 for upward compatibility. These
bits read 0.
Peripheral Interrupt Control
The Interrupt Control of each peripheral is controlled from
the status register using the interrupt mask. The status reg-
ister bits are ANDed to their corresponding interrupt mask
bits and the result is then ORed to generate the Interrupt
Source signal to the Advanced Interrupt Controller.
The interrupt mask is read in the Interrupt Mask Register
and is modified with the Interrupt Enable Register and the
Interrupt Disable Register. The enable/disable/status (or
mask) makes it possible to enable or disable peripheral
interrupt sources with a non-interruptible single instruction.
This eliminates the need for interrupt masking at the AIC or
Core level in real-time and multi-tasking systems.
Peripheral Data Controller
The AT91M42800 has an 8-channel PDC dedicated to the
two on-chip USARTs and to the two on-chip SPIs. One
PDC channel is connected to the receiving channel and
one to the transmitting channel of each peripheral.
The user interface of a PDC channel is integrated in the
memory space of each USART channel and in the memory
space of each SPI. It contains a 32-bit address pointer reg-
ister and a 16-bit count register. When the programmed
data is transferred, an end-of-transfer interrupt is generated
by the corresponding peripheral. See the USART section
and the SPI section for more details on PDC operation and
programming.
status of the peripheral.
registers. Writing a one in the Enable Register sets the
corresponding bit in the Status Register. Writing a one in
the Disable Register resets the corresponding bit and the
result can be read in the Status Register. Writing a bit to
zero has no effect. This register access method
maximizes the efficiency of bit manipulation, and enables
modification of a register with a single non-interruptible
instruction, replacing the costly read-modify-write
operation.
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