atxmega128a4-mu ATMEL Corporation, atxmega128a4-mu Datasheet - Page 20

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atxmega128a4-mu

Manufacturer Part Number
atxmega128a4-mu
Description
Atxmega16a4 8/16-bit Avr Xmega Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
13. PMIC - Programmable Multi-level Interrupt Controller
13.1
13.2
13.3
Table 13-1.
20
Program Address
(Base Address)
Features
Overview
Interrupt vectors
0x00C
0x01C
0x03D
0x03E
0x000
0x002
0x004
0x008
0x014
0x018
0x028
0x030
0x032
0x040
ATxmega A4
Reset and Interrupt Vectors
Source
RESET
IVEC_XOSCF_INT_vect
IVEC_PORTC_INT_base
IVEC_PORTR_INT_base
IVEC_DMAC_INT_base
IVEC_RTC_INT_base
IVEC_TWIC_INT_base
IVEC_TIMERC0_INT_base
IVEC_TIMERC1_INT_base
IVEC_SPIC_INT_vect
IVEC_USARTC0_INT_base
IVEC_USARTC1_INT_base
IVEC_AES_INT_vect
IVEC_NVM_INT_base
XMEGA A4 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
A Non-Maskable Interrupt (NMI) can detect oscillator failure.
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the module or peripherals base address and the specific interrupt's
offset address. The base addresses for the XMEGA A4 device is shown in
addresses for each interrupt available in the peripheral are described for each peripheral in the
XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector
is shown in
Separate interrupt vector for each interrupt
Short, predictable interrupt response time
Programmable Multi-level Interrupt Controller
Interrupt vectors can be moved to the start of the Boot Section
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
Table
13-1. The program address is the word address.
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interruptbase
DMA Controller Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI C Interrupt vector
USART 0 on port C Interrupt base
USART 1 on port C Interrupt base
AES Interrupt vector
Non-Volatile Memory INT base
Table
8069A–AVR–02/08
13-1. Offset

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