p89lpc9351 NXP Semiconductors, p89lpc9351 Datasheet - Page 54

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p89lpc9351

Manufacturer Part Number
p89lpc9351
Description
8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 8-bit Adc
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
P89LPC9351_1
Preliminary data sheet
8.10 Clock divider
8.11 Power-down and Idle mode
8.9 DAC output to a port pin with high output impedance
Each ADC’s DAC block can be output to a port pin. In this mode, the ADxDAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC (written to
ADxDAT3), the DAC output will appear on the channel 3 pin.
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the A/D interrupt is enabled. In
Power-down mode or Total Power-down mode, the A/D, PGA and temperature sensor do
not function. If the PGAs, temperature sensor or the A/D are enabled, they will consume
power. Power can be reduced by disabling the PGA, temperature sensor and A/D.
Rev. 01 — 19 November 2008
8-bit microcontroller with 8-bit ADC
P89LPC9351
© NXP B.V. 2008. All rights reserved.
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