lpc2294hbd144-01 NXP Semiconductors, lpc2294hbd144-01 Datasheet - Page 27

• Manufacturer Part Number: lpc2294hbd144-01
• Description: 16/32-bit Arm Microcontrollers 256 Kb Isp/iap Flash With Can, 10-bit Adc And External Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2292_2294_6
Product data sheet
6.19.7 Power control
6.19.8 APB bus
6.20.1 EmbeddedICE
6.20 Emulation and debugging
The LPC2292/2294 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode, and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to
properly at power-up (and its timing cannot be altered if it does not work since the APB
divider control registers reside on the APB bus), the default condition at reset is for the
APB bus to run at
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the APB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
The LPC2292/2294 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. EmbeddedICE protocol converter converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
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Rev. 06 — 10 December 2007
of the processor clock rate. The second purpose of the APB divider
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16/32-bit ARM microcontrollers with external memory interface
4
of the processor clock rate. Because the APB bus must work
LPC2292/LPC2294
© NXP B.V. 2007. All rights reserved.
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