lpc2388 NXP Semiconductors, lpc2388 Datasheet - Page 22

no-image

lpc2388

Manufacturer Part Number
lpc2388
Description
Single-chip 16-bit/32-bit Microcontroller; 512 Kb Flash With Isp/iap, Ethernet, Usb 2.0 Device/host/otg, Can, And 10-bit Adc/dac
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
lpc2388FBD
Manufacturer:
NXP
Quantity:
10 000
Part Number:
lpc2388FBD144
Manufacturer:
OMRON
Quantity:
5 000
Part Number:
lpc2388FBD144
Manufacturer:
KYCOERA
Quantity:
300
Part Number:
lpc2388FBD144
Manufacturer:
PHILIPS/
Quantity:
897
Part Number:
lpc2388FBD144
0
Company:
Part Number:
lpc2388FBD144
Quantity:
200
Company:
Part Number:
lpc2388FBD144
Quantity:
17
Part Number:
lpc2388FBD144,551
Quantity:
9 999
Part Number:
lpc2388FBD144,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
lpc2388FBD144,551
Manufacturer:
NXP
Quantity:
1 000
Part Number:
lpc2388FBD144,551
Manufacturer:
NXP
Quantity:
6 860
Part Number:
lpc2388FBD144,551
Manufacturer:
NXP
Quantity:
440
Part Number:
lpc2388FBD144,551
Manufacturer:
NXP
Quantity:
2 940
Part Number:
lpc2388FBD144.551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
LPC2388_0
Preliminary data sheet
7.10.1 Features
via the EMC, as well as the SRAM located on another AHB, if it is not being used by the
USB block. However, using memory other than the Ethernet SRAM, especially off-chip
memory, will slow Ethernet access to memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through standard RMII interface.
– PHY register access is available via the MIIM interface.
100 Base-FX, and 100 Base-T4.
pressure.
Redundancy Check (CRC) for transmit.
receive filters or a magic frame detection filter.
Rev. 00.02 — 28 January 2008
Fast communication chip
LPC2388
© NXP B.V. 2008. All rights reserved.
22 of 57

Related parts for lpc2388