lpc2478fet208 NXP Semiconductors, lpc2478fet208 Datasheet - Page 10

• Manufacturer Part Number: lpc2478fet208
• Description: Single-chip 16-bit/32-bit Micro; 512 Kb Flash, Ethernet, Can, Lcd, Usb 2.0 Device/host/otg, External Memory Interface Semiconductors
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
LPC2478_1
Preliminary data sheet
Symbol
P0[0] to P0[31]
P0[0]/RD1/TXD3/
SDA1
P0[1]/TD1/RXD3/
SCL1
P0[2]/TXD0
P0[3]/RXD0
P0[4]/I2SRX_CLK/
LCDVD[0]/RD2/
CAP2[0]
P0[5]/I2SRX_WS/
LCDVD[1]/TD2/
CAP2[1]
P0[6]/I2SRX_SDA/
LCDVD[8]/
SSEL1/MAT2[0]
Pin description
6.2 Pin description
Pin
94
96
202
204
168
166
164
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Ball
U15
T14
C4
D6
B12
C12
D13
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Type
I/O
I/O
I
O
I/O
I/O
O
I
I/O
I/O
O
I/O
I
I/O
I/O
O
I
I
I/O
I/O
O
O
I
I/O
I/O
O
I/O
O
Description
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 0 pins depends upon the pin function selected
via the Pin Connect block.
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input.
TXD3 — Transmitter output for UART3.
SDA1 — I
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output.
RXD3 — Receiver input for UART3.
SCL1 — I
P0[2] — General purpose digital input/output pin.
TXD0 — Transmitter output for UART0.
P0[3] — General purpose digital input/output pin.
RXD0 — Receiver input for UART0.
P0[4] — General purpose digital input/output pin.
I2SRX_CLK — I
by the slave. Corresponds to the signal SCK in the I
specification.
LCDVD[0] — LCD data.
RD2 — CAN2 receiver input.
CAP2[0] — Capture input for Timer 2, channel 0.
P0[5] — General purpose digital input/output pin.
I2SRX_WS — I
received by the slave. Corresponds to the signal WS in the I
specification.
LCDVD[1] — LCD data.
TD2 — CAN2 transmitter output.
CAP2[1] — Capture input for Timer 2, channel 1.
P0[6] — General purpose digital input/output pin.
I2SRX_SDA — I
by the receiver. Corresponds to the signal SD in the I
specification.
LCDVD[8] — LCD data.
SSEL1 — Slave Select for SSP1.
MAT2[0] — Match output for Timer 2, channel 0.
Rev. 01 — 6 July 2007
2
2
C1 clock input/output (this is not an open-drain pin).
C1 data input/output (this is not an open-drain pin).
[15]
[15]
[15]
2
S Receive word select. It is driven by the master and
2
2
S Receive clock. It is driven by the master and received
S Receive data. It is driven by the transmitter and read
[15]
[15]
[15]
Fast communication chip

LPC2478
S-bus
2
© NXP B.V. 2007. All rights reserved.
S-bus
2
S-bus
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