lh79520 NXP Semiconductors, lh79520 Datasheet
lh79520
Available stocks
Related parts for lh79520
lh79520 Summary of contents
Page 1
... RISC core provide high performance. To build an advanced portable device, advanced pro- cessing capability is required. This capability must come with increased performance in the display system and peripherals, and yet demand less power from batteries. The LH79520 is an integrated solution to fit these needs. 1 ...
Page 2
... LH79520 ORDERING INFORMATION Type number Name LH79520N0Q000B1 LQFP176 2 NXP Semiconductors Table 1. Ordering information Package Description plastic low profile quad flat package; 176 leads; body 1.4 mm Rev. 01 — 16 July 2007 System-on-Chip Version SOT1017-1 Preliminary data sheet ...
Page 3
... SDRAM DMA CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE COLOR LCD CONTROLLER ADVANCED HIGH PERFORMANCE BUS (AHB) ADVANCED LCD INTERFACE Figure 1. LH79520 block diagram Rev. 01 — 16 July 2007 LH79520 REAL TIME CLOCK GENERAL PURPOSE I/O I/O CONFIGURATION SYNCHRONOUS SERIAL PORT TIMER (4) WATCHDOG TIMER DUAL CHANNEL PWM ...
Page 4
... LH79520 PIN CONFIGURATION 4 NXP Semiconductors 1 132 LH79520 44 89 002aad212 Figure 2. LH79520 pin configuration Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
Page 5
... Output 145 DACK1 Output 144 DREQ1 Input Preliminary data sheet NXP Semiconductors Table 2. LH79520 Signal Descriptions DESCRIPTION MEMORY INTERFACE (MI) Address Signals Data Input/Output Signals SDRAM Clock Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs ...
Page 6
... LH79520 Table 2. LH79520 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 130 132 139 140 141 142 114 115 116 LCDVD[17:0] Output 117 118 119 121 122 123 124 126 127 137 LCDENAB Output 129 LCDFP Output 131 LCDLP Output 133 ...
Page 7
... System-on-Chip Table 2. LH79520 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 160 UARTRX1 Input 159 UARTTX1 Output 169 UARTRX2 Input 167 UARTTX2 Output 153 PA7 155 PA6 156 PA5 159 PA4 Input/Output 160 PA3 164 PA2 165 PA1 166 PA0 ...
Page 8
... LH79520 Table 2. LH79520 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 52 PG7 53 PG6 54 PG5 56 PG4 Input/Output 57 PG3 58 PG2 PG1 59 60 PG0 34 PH7 35 PH6 41 PH5 42 PH4 Input/Output 43 PH3 44 PH2 50 PH1 51 PH0 145 CTOUT1B Output RESET, CLOCK, AND POWER CONTROLLER (RCPC) 96 nRESETIN Input ...
Page 9
... System-on-Chip Table 2. LH79520 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE VDDC Power 113 136 154 45 120 VSSC Ground 138 158 VDD Power 85 100 125 143 161 VSS Ground 80 103 128 149 168 91 VDDA Power ...
Page 10
... LH79520 NUMERICAL PIN LIST Table 3. LH79520 Numerical Pin List FUNCTION AT PIN NO. FUNCTION 2 FUNCTION 3 RESET 1 nTSTA 2 A25 3 A24 4 A23 5 A22 6 A21 7 A20 8 VDD 9 A19 10 A18 11 A17 12 A16 13 VSS 14 A15 15 A14 16 A13 17 A12 18 VDD 19 A11 20 A10 VSS ...
Page 11
... System-on-Chip Table 3. LH79520 Numerical Pin List (Cont’d) FUNCTION AT PIN NO. FUNCTION 2 FUNCTION 3 RESET 39 nWE 40 VDDC 41 PH5 nCS6 42 PH4 nCS5 43 PH3 nCS4 44 PH2 nCS3 45 VSSC 46 nCS2 47 nCS1 48 nCS0 49 VDD 50 PH1 D31 51 PH0 D30 52 PG7 D29 53 PG6 D28 54 PG5 D27 55 VSS 56 PG4 ...
Page 12
... LH79520 Table 3. LH79520 Numerical Pin List (Cont’d) FUNCTION AT PIN NO. FUNCTION 2 FUNCTION 3 RESET VSS VDD CLKINSEL 89 XTAL32IN 90 XTAL32OUT 91 VDDA 92 VSSA 93 XTALIN 94 XTALOUT 95 VDDC 96 nRESETIN 97 nRESETOUT 98 CLKIN UARTCLK 99 PF1 CLKEN 100 VDD 101 PF0 ...
Page 13
... System-on-Chip Table 3. LH79520 Numerical Pin List (Cont’d) FUNCTION AT PIN NO. FUNCTION 2 FUNCTION 3 RESET 117 PD6 LCDVD8 118 PD5 LCDVD7 119 PD4 LCDVD6 120 VSSC 121 PD3 LCDVD5 122 PD2 LCDVD4 123 PD1 LCDVD3 124 PD0 LCDVD2 125 VDD 126 LCDVD1 ...
Page 14
... LH79520 Table 3. LH79520 Numerical Pin List (Cont’d) FUNCTION AT PIN NO. FUNCTION 2 FUNCTION 3 RESET 156 PA5 CLKOUT 157 PWM1 DEOT1 158 VSSC 159 PA4 UARTTX1 160 PA3 UARTRX1 161 VDD 162 UARTIRTX0 UARTTX0 163 UARTIRRX0 UARTRX0 164 PA2 SSPFRM 165 PA1 SSPCLK ...
Page 15
... Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) Panel Data Clock External Clock Input Digital Supply Enable/Gate Driver Clock Data Enable/ Line Start Pulse (Left) Reverse Signal (AD-TFT, HR-TFT only) Rev. 01 — 16 July 2007 LH79520 ALL TFT: PALETTE ALL TFT: ALL TFT: DATA OR 5:5:5+I ...
Page 16
... The processor is a member of the ARM7T family of processors. For more information, see the ARM docu- ment, ‘ARM720T (Rev 3) Technical Reference Manual’, available on NXP’s’s website at www.nxp.com. The LH79520 MMU provides a means to map Phys- ical Memory (PA) addresses to virtual memory addresses. This allows physical memory, which is con- 16 ...
Page 17
... STATIC MEMORY CONTROLLER (SMC) The SMC provides the interface between the internal bus and external (off-chip) memory devices. The LH79520 boots from 16-bit memory. The SMC address space is divided into eight memory banks each. The SMC supports: • Static Memory-mapped Devices including RAM, ROM, Flash, and Burst ROM • ...
Page 18
... The 18 NXP Semiconductors Advanced LCD Interface peripheral also provides a bypass mode that allows the LH79520 to interface to the built-in timing ASIC in standard TFT and STN panels. Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous ...
Page 19
... This logic reduces the interrupt response time for IRQ type interrupts compared to solutions using software polling to determine the high- est priority interrupt source. This significantly improves the real-time capabilities of the LH79520 in embedded control applications. • 20 internal and eight external interrupt sources – Individually maskable – ...
Page 20
... Reset, Clock, and Power Controller (RCPC) The RCPC generates the various clock signals for the operation of the LH79520 and provides for an orderly start-up after power-on and during a wake-up from one of the power saving operating modes. The RCPC allows the software to individually select the frequency of the various on-chip clock signals as required to operate the chip in the most power-efficient mode ...
Page 21
... The features of the Watchdog Timer are: • Driven by the bus clock • 16 programmable time-out periods: 2 clock cycles • Generates a system reset (resets LH79520 FIQ Interrupt whenever a time-out period is reached • Software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes • ...
Page 22
... LH79520 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER DC Core Supply Voltage DC I/O Supply Voltage DC Analog Supply Voltage Storage Temperature NOTE: These stress ratings are only for transient conditions. Oper- ation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. ...
Page 23
... RATING UNIT 3.0 to 3.6 V 1.62 to 1.98 V VSS to VDD VDD/2 V Rev. 01 — 16 July 2007 LH79520 CONDITIONS NOTES VIT+ – VIT- IOH = -50 µ IOH = - IOH = - IOH = -8 mA IOL = 50 µ IOL = IOL = 4 mA ...
Page 24
... SIGNAL (O) INPUT SIGNAL (I) 24 NXP Semiconductors For outputs from the LH79520, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 8. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the ris- ing edge of the reference clock signal ...
Page 25
... Rev. 01 — 16 July 2007 LH79520 MAX. DESCRIPTION Data Output Valid, following Address Valid Data Output Invalid, following Address Valid Data Input Valid, following Address Valid Data Input Valid, following Address Valid (nWAIT states) Chip Select Output Valid, ...
Page 26
... LH79520 Table 8. AC Signal Characteristics (Commercial) (Cont’d) SIGNAL TYPE LOAD DRIVE SSPFRM Output SSPEN Output SSPTX Output SSPRX Input INTR[5:0] Input NOTES: 1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode, and held Active for a minimum Edge Sensitive Mode ...
Page 27
... RATING UNIT 3.0 to 3.6 V 1.62 to 1.98 V VSS to VDD VDD/2 V Rev. 01 — 16 July 2007 LH79520 CONDITIONS NOTES VIT+ – VIT- IOH = -50 µ IOH = - IOH = - IOH = -8 mA IOL = 50 µ IOL = IOL = 4 mA ...
Page 28
... LH79520 CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 9 were derived under the conditions presented here. Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: • ...
Page 29
... Rev. 01 — 16 July 2007 LH79520 DESCRIPTION Data Output Valid, following Address Valid Data Output Invalid, following Address Valid Data Input Valid, following Address Valid (1 WAIT state) Data Input Valid, following Address Valid (nWAIT states) ...
Page 30
... LH79520 Table 11. AC Signal Characteristics (Cont’d)(Industrial) SIGNAL TYPE LOAD DRIVE nSDCS[1:0] Output SDCLK Output SSPFRM Output SSPEN Output SSPTX Output SSPRX Input INTR[5:0] Input NOTES: 1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode, and held Active for a minimum Edge Sensitive Mode ...
Page 31
... External Static Memory Read, with two Wait States. The signal tIDD is shown without a setup time, as measurements are made from the Address Valid point and HCLK is an internal signal, shown for reference only. Rev. 01 — 16 July 2007 LH79520 31 ...
Page 32
... LH79520 32 NXP Semiconductors Figure 11. nWait Assertion Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
Page 33
... System-on-Chip Figure 12. External Static Memory Write, One Wait State Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 33 ...
Page 34
... LH79520 Figure 13. External Static Memory Read, One Wait State 34 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
Page 35
... System-on-Chip Figure 14. External Static Memory Write, Two Wait States Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 35 ...
Page 36
... LH79520 Figure 15. Synchronous Serial Port Waveform 36 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
Page 37
... OHXXX READ OVXXX BANK, tISD tIHD COLUMN tOVA DATA n DATA Figure 16. SDRAM Burst Read tOVC0 tOVXXX tOHXXX ACTIVE tOVA BANK, ROW tOVA Rev. 01 — 16 July 2007 LH79520 DATA DATA LH79520-35 WRITE BANK, COLUMN DATA tOVD tOHD 79520-36 37 ...
Page 38
... LH79520 External DMA Handshake Signal Timing DREQ TIMING As Figure 18 shows, once asserted, DREQ0 or DREQ1 must not transition from LOW to HIGH again until after nDACK0 or DACK1 has been asserted. DACK/DEOT TIMING These timing diagrams indicate when nDACK0, DACK1, DEOT0 and DEOT1 occur in relation to an external bus access to/from the external peripheral that requested the DMA transfer ...
Page 39
... Note) A[23:0] D[15:0] nCSx nWEN nBLE[1:0] nOE nDACK0/ DEOT0/DEOT1 DACK1 NOTE: * HCLK is an internal signal provided for reference only. Figure 20. Write, from Memory to Peripheral, Burst Size = 1 Preliminary data sheet NXP Semiconductors ADDRESS DATA ADDRESS DATA Rev. 01 — 16 July 2007 LH79520 79520-156 79520-157 39 ...
Page 40
... LH79520 * HCLK ADDRESS A[23:0] D[31:0] nCSx nWEN nBLE[1:0] nOE n DACK0/DEOT0/DEOT1 DACK1 NOTE: * HCLK is an internal signal, provided for reference only. Figure 21. Read, Peripheral to Memory: Peripheral Burst Size = 4 40 NXP Semiconductors DATA #1 DATA #2 DATA #3 Rev. 01 — 16 July 2007 System-on-Chip DATA #4 79520-169 Preliminary data sheet ...
Page 41
... System-on-Chip Figure 22. Write, Memory to Peripheral: Burst Size = 4; Destination Width > External Access Width Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 41 ...
Page 42
... LH79520 Color LCD Controller System Timing Waveforms This section contains typical output waveform dia- grams. STN HORIZONTAL TIMING Figure 23 presents typical horizontal timing wave- forms for STN panels. Figure 23 shows that the CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and utilized to produce the LCDDCLK output. ...
Page 43
... System-on-Chip Figure 23. STN Horizontal Timing Diagram Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 43 ...
Page 44
... LH79520 44 NXP Semiconductors Figure 24. STN Vertical Timing Diagram Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
Page 45
... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 25. TFT Horizontal Timing Diagram Rev. 01 — 16 July 2007 LH79520 45 ...
Page 46
... LH79520 46 NXP Semiconductors Figure 26. TFT Vertical Timing Diagram Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...
Page 47
... LCDLP (HORIZONTAL SYNC PULSE) 135 LCDCLS 119 LCDPS 142 LCDREV NOTE: Circled numbers are LH79520 pin numbers. Figure 27. AD-TFT and HR-TFT Horizontal Timing Diagram LCDSPS (Vertical Sync) 1.5 µ µs LCDCLS (Gate Driver Clock) LCDVD[17:0] (LCD DATA) NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz. ...
Page 48
... LH79520 Reset, Clock, and Power Controller (RCPC) Waveforms Figure 29 shows the method the LH79520 uses when coming out of Reset or Power On. Figure 30 shows external reset timing, and Table 13 gives the timing parameters. PARAMETER tOSC32 Oscillator stabilization time after Power Up (VDDC = VDDCMIN) tOSC14 ...
Page 49
... SoC). Assuring Proper Reset Behavior A separate reset for the TAP controller and power- on was designed into the LH79520 to give the Designer control over how the chip boots up and to be useful for bringing up software and hardware using E-ICE. ...
Page 50
... Note that the VSSA pin specifically does not have a connection to the circuit board ground. The LH79520 PLL circuit has an internal DC ground connection to VSS (GND), so the external VSSA pin must NOT be connected to the circuit board ground, but only to the filter components ...
Page 51
... Figure 33. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT) Preliminary data sheet NXP Semiconductors Figure 34 shows the suggested external components for the 14.7456 MHz crystal circuit to be used with the NXP LH79520. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics. ENABLE XTAL32IN Y1 32 ...
Page 52
... LH79520 INTERNAL TO THE LH79520 EXTERNAL TO THE LH79520 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance ...
Page 53
... scale (1) ( 0.20 20.2 20.2 22.2 22.2 0.4 0.09 19.8 19.8 21.8 21.8 REFERENCES JEDEC JEITA Rev. 01 — 16 July 2007 SOT1017 θ detail X (1) ( 0.75 1.5 1.5 1 0.2 0.07 0.08 0.45 1.3 1.3 EUROPEAN ISSUE DATE PROJECTION 07-07-07 07-07-07 LH79520 θ ° 7 ° ...
Page 54
... LH79520 NOTE: Dimensions in mm. 54 NXP Semiconductors 21.25 0.4 17.2 Figure 36. Recommended PCB Footprint Rev. 01 — 16 July 2007 System-on-Chip 1.70 79520-155 Preliminary data sheet ...
Page 55
... REVISION HISTORY Document ID Release date Data sheet status LH79520_N_1 20070716 Preliminary data sheet Modifications: • First NXP version based on the LH79520 data sheet of 20060330 Preliminary data sheet NXP Semiconductors Table 14. Revision history Change notice Supersedes - LH79520 Data Sheet v1_3 Rev. 01 — 16 July 2007 ...
Page 56
... LH79520 1. Legal information 1.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. ...
Page 57
... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...
Page 58
... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...
Page 59
... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...