zlf645e0s2832g ZiLOG Semiconductor, zlf645e0s2832g Datasheet - Page 156

no-image

zlf645e0s2832g

Manufacturer Part Number
zlf645e0s2832g
Description
Crimzon Infrared Microcontrollers Zlf645 Series Flash Mcus With Learning Amplification
Manufacturer
ZiLOG Semiconductor
Datasheet
PS026407-0408
To configure a Port 3 input pin as an SMR3 event source set the corresponding SMR3
register bit. By default, a Stop Mode Recovery event occurs when the pin’s state is zero.
After a Port 3 pin is configured as an SMR3 source, any subsequent read from or write to
the P2 register latches the read or written value for reference. A Stop Mode Recovery
event occurs when the pin’s state differs from the last reference value latched. The SMR3
source logic is displayed in
The program can read register bits SMR4[3:2] to determine whether the Port 3 pins trigger
a Stop Mode Recovery on a change from the last read value (SMR4[3:2]=01), or on a
change from the last written value (SMR4[3:2]=10). Software can clear SMR4[3:2] to 00
to restore the default behavior (configured pins trigger when their state is 0).
The SMR3 register is summarized in
After the following example code is executed, a 1 on P30 will wake the part from STOP
mode.
After the following example code is executed when the value of P3 is 00h, a 1 on P30 will
wake the part from STOP mode.
LD SMR3, #%01
LD P3, #%00
NOP
STOP
LD SMR3, #%01
LD R6, P3
NOP
STOP
;Select P30 from SMR3.
;Write 00h to Port 3, so the P30 reference
;value is 0, and a 1 on P30 wakes the part.
;Select P30 for SMR3.
;If a 0 is read from Port 3, the P30 reference
;value is 0, so a 1 on P30 wakes the part.
Figure
47.
Table 70 on page
141.
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
Product Specification
148

Related parts for zlf645e0s2832g