mc9s08gt16a Freescale Semiconductor, Inc, mc9s08gt16a Datasheet - Page 229

• Manufacturer Part Number: mc9s08gt16a
• Description: Hcs08 Microcontrollers 8-bit Microcontroller Family
• Manufacturer: Freescale Semiconductor, Inc

14.3.3
For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map onto
ATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB).
For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7–0 map
onto ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB).
The ATD 10-bit conversion results are stored in two 8-bit result registers, ATDRH and ATDRL. The result
data is formatted either left or right justified where the format is selected using the DJM control bit in the
ATDC register. The 10-bit result data is mapped either between ATDRH bits 7–0 and ATDRL bits 7–6 (left
justified), or ATDRH bits 1–0 and ATDRL bits 7–0 (right justified).
For 8-bit conversions, the 8-bit result is always located in ATDRH bits 7–0, and the ATDRL bits read 0.
For 10-bit conversions, the six unused bits always read 0.
The ATDRH and ATDRL registers are read-only.
14.3.4
Freescale Semiconductor
ATDPE[7:0]
Reset
ATD1RH
ATD1RH
Field
7:0
7
9
7
W
R
ATDPE7
ATD Result Data (ATDRH, ATDRL)
ATD Pin Enable (ATDPE)
6
6
ATD Pin 7–0 Enables — The ATD pin enable register allows the pins dedicated to the ATD module to be
configured for ATD usage. A write to this register will abort the current conversion but will not initiate a new
conversion. If the ATDPEx bit is 0 (disabled for ATD usage) but the corresponding analog input channel is
selected via the ATDCH bits, the ATD will not convert the analog input but will instead convert V
zeroes in the ATD result registers.
0 Pin disabled for ATD usage.
1 Pin enabled for ATD usage.
0
7
5
5
ATDPE6
4
4
0
6
3
3
Table 14-7. ATDSC Register Field Descriptions
Figure 14-9. ATD Pin Enable Register (ATDPE)
RESULT
MC9S08GT16A/GT8A Data Sheet, Rev. 1
ATDPE5
2
2
Figure 14-8. Right-Justified Mode
Figure 14-7. Left-Justified Mode
0
5
1
1
9
ATDPE4
0
0
0
4
Description
ATD1RL
ATD1RL
7
7
ATDPE3
3
0
6
0
6
RESULT
5
5
ATDPE2
Analog-to-Digital Converter (S08ATDV3)
4
4
0
2
3
3
ATDPE1
2
2
0
1
REFL
1
1
placing
ATDPE0
0
0
0
0
0
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