mc9s08ac128 Freescale Semiconductor, Inc, mc9s08ac128 Datasheet - Page 30

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mc9s08ac128

Manufacturer Part Number
mc9s08ac128
Description
8-bit Hcs08 Central Processor Unit Cpu
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 3 Electrical Characteristics and Timing Specifications
3.11
Table 3-14
30
and
SPI Characteristics
1
2
3
4
5
Num
Figure 3-15
Refer to
All timing is shown with respect to 20% V
Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
Time to data active from high-impedance state.
Hold time to high-impedance state.
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
10
11
1
2
3
4
5
6
7
8
9
1
Figure 3-15
C
through
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Master and Slave
Clock (SPSCK) low time Master
and Slave
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
Figure 3-18
through
Characteristic
Table 3-14. SPI Electrical Characteristic
MC9S08AC128 Series Data Sheet, Rev. 1
Figure
Preliminary — Subject to Change
describe the timing requirements for the SPI system.
4
5
3
3-18.
2
Master
Master
Master
Master
Master
Master
Master
Master
DD
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
and 70% V
Symbol
t
t
t
t
t
t
t
t
SCKH
SCKL
t
t
SI(M)
HI(M)
t
t
SI(S)
HI(S)
Lead
Lead
t
t
t
t
t
SCK
SCK
f
f
Lag
Lag
SO
SO
HO
HO
t
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI
1/2 t
1/2 t
f
Bus
SCK
SCK
Min
–10
–10
1/2
1/2
dc
30
30
30
30
25
25
/2048
2
4
0
– 25
– 25
f
f
2048
Bus
Bus
Max
1/2
1/2
40
40
/2
/4
Freescale Semiconductor
t
t
t
t
Unit
SCK
SCK
SCK
SCK
t
t
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc

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