mc9s12c32mpb16 Freescale Semiconductor, Inc, mc9s12c32mpb16 Datasheet - Page 257
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mc9s12c32mpb16
Manufacturer Part Number
mc9s12c32mpb16
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12C32MPB16.pdf
(680 pages)
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9.3.2.2
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: anytime
Write: anytime except when PLLSEL = 1
9.3.2.3
This register is reserved for factory testing of the CRGV4 module and is not available in normal modes.
Read: always reads 0x0000 in normal modes
Write: unimplemented in normal modes
Freescale Semiconductor
Module Base + 0x0001
Module Base + 0x0002
Reset
Reset
W
W
R
R
CRG Reference Divider Register (REFDV)
Reserved Register (CTFLG)
0
0
0
0
7
7
Write to this register initializes the lock detector bit and the track detector
bit.
Writing to this register when in special mode can alter the CRGV4
functionality.
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 9-5. CRG Reference Divider Register (REFDV)
Figure 9-6. CRG Reserved Register (CTFLG)
MC9S12C-Family / MC9S12GC-Family
0
0
0
0
5
5
Rev 01.23
NOTE
NOTE
0
0
0
0
4
4
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
REFDV3
0
0
0
3
3
REFDV2
0
0
0
2
2
REFDV1
0
0
0
1
1
REFDV0
0
0
0
0
0
257
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