cop87l84bc National Semiconductor Corporation, cop87l84bc Datasheet - Page 11

• Manufacturer Part Number: cop87l84bc
• Description: 8-bit Cmos Otp Microcontrollers With 16k Memory, Comparators, And Can Interface
• Manufacturer: National Semiconductor Corporation

Oscillator Circuits
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
Table 1 shows the component values required for various
standard crystal values.
Control Registers
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
Bit 7
Bit 7
(k )
T1C3
HC
TABLE 1. Crystal Oscillator Configuration, T
R1
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
0
0
0
C
(M )
T1C2
FIGURE 7. Crystal Oscillator Diagram
R2
1
1
1
T1PNDA
Half Carry Flag
Carry Flag
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T1C1
(pF)
200
C1
30
30
T1ENA
100–150
T1C0
30–36
30–36
(pF)
C2
EXPND
DS101137-7
(Continued)
MSEL
CKI Freq.
(MHz)
0.455
BUSY
10
4
IEDG
EXEN
Conditions
SL1
A
V
V
V
CC
CC
CC
= 25˚C
= 5V
= 5V
= 5V
Bit 0
GIE
SL0
Bit 0
11
Reserved
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
Timers
The device contains a very versatile set of timers (T0, T1,
and an 8-bit PWM timer). All timers and associated
autoreload/capture registers power up containing random
data.
Figure 8 shows a block diagram for timers T1 and T0 on the
device.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
The IDLE Timer T0 can generate an interrupt when the thir-
teenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4.096 ms at the maximum
clock frequency (t
terrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.
TIMER T1
The device has a powerful timer/counter block, T1.
The timer block consists of a 16-bit timer, T1, and two sup-
porting 16-bit autoreload/capture registers, R1A and R1B.
The timer block has two pins associated with it, T1A and
T1B. The pin T1A supports I/O required by the timer block,
Bit 7
T1ENA
EXPND
BUSY
EXEN
GIE
Reserved This bit is reserved and must be zero.
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
T1ENB
Exit out of the Idle Mode (See Idle Mode description)
Start up delay out of the HALT mode
LPEN
or T1A Input capture edge
Timer T1 Interrupt Enable for Timer Underflow
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
T0PND
c
= 1 µs). A control flag T0EN allows the in-
T0EN
µWPND
c
. The user cannot read or
µWEN
T1PNDB
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T1ENB
Bit 0