cop87l42rj National Semiconductor Corporation, cop87l42rj Datasheet - Page 13

• Manufacturer Part Number: cop87l42rj
• Description: 8-bit Cmos Otp Microcontrollers With 4k Or 32k Memory And Comparator
• Manufacturer: National Semiconductor Corporation

8-Bit Prescaler
8-Bit WD Counter
WDREN Bit
WDUDF Bit
WDTEN Signal
WATCHDOG
flag. The bit is cleared upon external reset, load to the 8-bit
counter, or going into the HALT mode. It is a read only bit.
WDREN: WD Reset Enable
WDREN bit resides in a separate register (bit 0 of WDREG).
This bit enables the WATCHDOG timer to generate a reset.
The bit is cleared upon external reset. The bit under software
Modulator/Timer
The Modulator/Timer contains an 8-bit counter and an 8-bit
autoreload register (MODRL address 0CF Hex). The
Modulator/Timer has two modes of operation, selected by
the control bit MC3. The Modulator/Timer Control bits MC1,
MC2 and MC3 reside in CNTRL2 Register.
MODE 1: MODULATOR
The Modulator is used to generate high frequency pulses on
the modulator output pin (L7). The L7 pin should be config-
ured as an output. The number of pulses is determined by
the 8-bit down counter. Under software control the modulator
input clock can be either CKI or tC. The tC clock is derived by
dividing down the oscillator clock by a factor of 10. Three
control bits (MC1, MC2, and MC3) are used for the
Modulator/Timer output control. When MC2 = 1 and MC3 =
1, CKI is used as the modulator input clock. When MC2 = 0,
and MC3 = 1, tC is used as the modulator input clock. The
user loads the counter with the desired number of counts
(256 max) and sets MC1 to start the counter. The modulator
autoreload register is loaded with n-1 to get n pulses. CKI or
tc pulses are routed to the modulator output (L7) until the
counter underflows ( Figure 12 ). Upon underflow the hard-
ware resets MC1 and stops the counter. The L7 pin goes low
and stays low until the counter is restarted by the user pro-
gram. The user program has the responsibility to timeout the
low time. Unless the number of counts is changed, the user
program does not have to load the counter each time the
counter is started. The counter can simply be started by set-
ting the MC1 bit. Setting MC1 by software will load the
counter with the value of the autoreload register. The soft-
ware can reset MC1 to stop the counter.
MODE 2: PWM TIMER
The counter can also be used as a PWM Timer. In this mode,
an 8-bit register is used to serve as an autoreload register
(MODRL).
a. 50% Duty Cycle:
When MC1 is 1 and MC2, MC3 are 0, a 50% duty cycle free
running signal is generated on the L7 output pin ( Figure 13 ).
The L7 pin must be configured as an output pin. In this mode
the 8-bit counter is clocked by tC. Setting the MC1 control bit
Parameter
(Continued)
Unchanged
Unchanged
HALT
Mode
FF
FF
0
TABLE 6. WATCHDOG Control/Status
13
Unchanged
Unchanged
Reset
WD
control can be written to only once (once written to, the hard-
ware does not allow the bit to be changed during program
execution).
WDREN = 1 WATCHDOG reset is enabled.
WDREN = 0 WATCHDOG reset is disabled.
Table 6 shows the impact of WATCHDOG Reset and Exter-
nal Reset on the Control/Status bits.
by software loads the counter with the value of the autore-
load register and starts the counter. The counter underflow
toggles the (L7) output pin. The 50% duty cycle signal will be
continuously generated until MC1 is reset by the user pro-
gram.
b. Variable Duty Cycle:
When MC3 = 0 and MC2 = 1, a variable duty cycle PWM sig-
nal is generated on the L7 output pin. The counter is clocked
by tC. In this mode the 16-bit timer T1 along with the 8-bit
down counter are used to generate a variable duty cycle
PWM signal. The timer T1 underflow sets MC1 which starts
the down counter and it also sets L7 high (L7 should be con-
figured as an output).When the counter underflows the MC1
control bit is reset and the L7 output will go low until the next
timer T1 underflow. Therefore, the width of the output pulse
is controlled by the 8-bit counter and the pulse duration is
controlled by the 16-bit timer T1 ( Figure 14 ). Timer T1 must
be configured in “PWM Mode/Toggle TIO Out” (CNTRL1 Bits
7,6,5 = 101).
Table 7 shows the different operation modes for the
Modulator/Timer.
Note: MC1, MC2 and MC3 control bits are cleared upon reset.
FF
FF
0
MC3
0
0
0
1
1
CNTRL2(00CC)
Control Bits in
MC2
0
0
1
0
1
TABLE 7. Modulator/Timer Modes
MC1
X
X
X
0
1
Reset
EXT
FF
FF
0
0
0
Normal I/O
50% Duty Cycle Mode (Clocked
by tc)
Variable Duty Cycle Mode
(Clocked by tc) Using Timer 1
Underflow
Modulator Mode (Clocked by tc)
Modulator Mode (Clocked by
CKI)
Operation Mode
L7 Function
User Value
No Effect
Counter
Load
FF
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