cop87l42rj National Semiconductor Corporation, cop87l42rj Datasheet - Page 15

• Manufacturer Part Number: cop87l42rj
• Description: 8-bit Cmos Otp Microcontrollers With 4k Or 32k Memory And Comparator
• Manufacturer: National Semiconductor Corporation

Input Offset Voltage
Input Common Mode Voltage Range
Voltage Gain
DC Supply Current (when enabled)
Response Time
Note 8: For comparator output current characteristics see L-Port specs.
Modulator/Timer
Comparator
The device has one differential comparator. Ports L0–L2 are
used for the comparator. The output of the comparator is
brought out to a pin. Port L has the following assignments:
L0 Comparator output
L1 Comparator negative input
L2 Comparator positive input
THE COMPARATOR STATUS/CONTROL BITS
These bits reside in the CNTRL2 Register (Address 0CC)
CMPEN Enables comparator (“1” = enable)
CMPRD Reads comparator output internally
Multi-Input Wake Up
The Multi-Input Wakeup feature is used to return (wakeup)
the device from the HALT mode. Figure 15 shows the
Multi-Input Wakeup logic.
This feature utilizes the L Port. The user selects which par-
ticular L port bit or combination of L Port bits will cause the
device to exit the HALT mode. Three 8-bit memory mapped
Parameters
TABLE 8. DC and AC Characteristics (Note 8) 4.5V
(Continued)
FIGURE 14. Mode 2b: Variable Duty Cycle Output
0.4V
V
TBD mV Step,
TBD mV Overdrive, 100 pF Load
CC
= 5.5V
<
V
IN
Conditions
<
V
CC
−1.5V
15
CMPOE Enables comparator output to pin L0
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power the program
should also disable the comparator before the device enters
the HALT mode.
The user program must set up L0, L1 and L2 ports correctly
for comparator Inputs/Output: L1 and L2 need to be config-
ured as inputs and L0 as output. Table 8 shows the DC and
AC characteristics for the comparator.
registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPND are
used in conjunction with the L port to implement the
Multi-Input Wakeup feature.
All three registers Reg:WKEN, Reg:WKPND, and Reg-
:WKEDG are read/write registers, and are cleared at reset,
except WKPND. WKPND is unknown on reset.
The user can select whether the trigger condition on the se-
lected L Port pin is going to be either a positive edge (low to
high transition) or a negative edge (high to low transition).
V
CC
(CMPEN = 1, CMPOE=X)
(“1”=enable), CMPEN bit must be set to enable
this function. If CMPEN=0, L0 will be 0.
5.5V, −40˚C
Min
0.4
DS012529-18
300k
Typ
±
10
T
A
+85˚C
DS012529-17
V
CC
Max
±
250
1
25
−1.5
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Units
V/V
mV
µA
µs
V