cop888ek National Semiconductor Corporation, cop888ek Datasheet - Page 17

• Manufacturer Part Number: cop888ek
• Description: 8-bit Cmos Rom Based Microcontrollers With 8k Memory, Comparator, And Single-slope A/d Capability
• Manufacturer: National Semiconductor Corporation

Control Registers
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
T2CNTRL Register (Address X'00C6)
The T2CNTRL control register contains the following bits:
Bit 7
Bit 7
T2C3
Bit 7
HC
Rsvd
MSEL
IEDG
SL1 & SL0
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA
EXPND
BUSY
EXEN
GIE
Rsvd
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
T1ENB
T2C3
T2C2
T2C1
T2C0
C
T2C2
LPEN
T1PNDA
Half Carry Flag
Carry Flag
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
This bit is reserved and must be zero
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
ture edge
Timer T1 Interrupt Enable for T1B Input capture
edge
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
Timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3
T2C1
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T0PND
T2C0
T1ENA
T2
T0EN
T2PNDA
Start/Stop
EXPND
µWPND
(Continued)
T2ENA
µWEN
BUSY
control
T2PNDB
T1PNDB
EXEN
in
T2ENB
T1ENB
timer
Bit 0
GIE
Bit 0
Bit 0
17
T3CNTRL Register (Address X'00B6)
The T3CNTRL control register contains the following bits:
Timers
The device contains a very versatile set of timers (T0, T1,
T2, T3). All timers and associated autoreload/capture regis-
ters power up containing random data.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
The IDLE Timer T0 can generate an interrupt when the thir-
teenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
clock frequency (t
terrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.
TIMER T1, TIMER T2 AND TIMER T3
The device has a set of three powerful timer/counter blocks,
T1, T2 and T3. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the three timer blocks, T1, T2 and T3 are identical, all
comments are equally applicable to any of the three timer
blocks.
j
j
j
T3C3
Bit 7
T2PNDA
T2ENA
T2PNDB
T2ENB
T3C3
T3C2
T3C1
T3C0
T3PNDA
T3ENA
T3PNDB
T3ENB
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
T3C2
Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
Timer T3 mode control bit
Timer T3 mode control bit
Timer T3 mode control bit
Timer
modes 1 and 2, T3 Underflow Interrupt Pend-
ing Flag in timer mode 3
Timer T3 Interrupt Pending Flag (Autoreload
RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
Timer T3 Interrupt Pending Flag for T3B cap-
ture edge
Timer T3 Interrupt Enable for Timer Underflow
or T3B Input capture edge
T3C1
c
= 1 µs). A control flag T0EN allows the in-
T3C0
T3
T3PNDA
Start/Stop
c
. The user cannot read or
T3ENA
control
T3PNDB
www.national.com
in
T3ENB
timer
Bit 0