an87c196kt Intel Corporation, an87c196kt Datasheet - Page 32

• Manufacturer Part Number: an87c196kt
• Description: Advanced 16-bit Chmos Microcontroller
• Manufacturer: Intel Corporation

87C196KT 87C196KS
87C196KT KS ERRATA
The following is a list of all known functional devia-
tions for 87C196KT KS devices B-step and later
devices can be identified by a special mark following
the eight digit FPO number on the top of the pack-
age For C-step devices this mark is a ‘‘C’’
1 HOLD OR READY DURING DIVIDE (A-step)
2 P2 7 (CLKOUT) (A-step)
3 P2 REG 7 AND P6 REG 4 THROUGH P6
4 INDIRECT SHIFT INSTRUCTION (A-step)
5 INTERNAL RAM POWERDOWN LEAKAGE
6 INST PIN (A-step)
32
There is a bug in the DIV and DIVB (signed di-
vide) instructions such that if the following 2 con-
ditions are met there may be an error of 1 in the
quotient
a) HOLD or READY is asserted during the first
b) HOLD or READY duration is 16 state times for
Port 2 7 (CLKOUT) does not operate in open
drain mode
REG 7 CLEARED (A-step)
P2 REG 7 is cleared when P2 SSEL 7 bit is
changed from a 1 to a 0 (special function to
LSIO) P6 Reg 4 – 7 is cleared when the corre-
sponding P6 SSEL 4 – 7 is changed from a 1 to
a 0
The upper three bits of the byte register holding
the shift count are not masked completely If the
shift count register has the value 32 x n where n
times The above condition results in NO shift
taking place
(A-step)
If an invalid address is applied to the internal
RAM during power-down the address lines float
This can cause increased current consumption
during power-down To insure a valid address on
the internal RAM execute the idle power-down
instruction from internal RAM
On A-step devices the INST pin is pulled medium
low for approx 200 ns after RESET and then
pulled weakly HIGH until P5SSEL is written to
This is corrected on B-step devices where the
INST pin is pulled medium low for approx 200 ns
after RESET and is then pulled weakly LOW until
P5SSEL is written to
e
state of execution of the DIV and DIVB in-
struction
the DIVB or 24 state times for a DIV instruc-
tion
1 3 5 or 7 the operand wil be shifted 32
7 REGISTER
8 BUS TIMING MODES 1 AND 2 (A-step B-step)
9 V
10 CLKOUT DURING RESET (A-step B-step
B-step)
If a write is performed to a byte word location
within the SFR range of 1F60h to 1FFFh the
data to be written is also written to a correspond-
ding location located within the REGISTER RAM
space 360h to 3FFh To determine the address
of the REGISTER RAM location that is overwrit-
ten an offset of 1C00h can be subtracted from
the byte word addressed in the SFR range
Bus timing modes 1 and 2 are not featured or
specified on A-step and B-step parts On C-step
parts Mode 1 is selected by setting bits MSEL1
Mode 2 is similarly selected by setting MSEL1
1 and MSEL0
Mode 1 and Mode 2 as follows (for actual values
see the Bus Mode 1 and Bus Mode 2 AC Charac-
teristics in this data sheet)
Mode 1 RD WR advanced 1 T
Mode 2 RD WR advanced 1 T
A- and B-step parts are capable of V
the target values of V
e
b
e b
C-step)
For all steppings of the 87C196KT
CLKOUT function during RESET (P2 7) differs
from the 87C196KR C-step During RESET on
the 87C196KT CLKOUT does not toggle and
remains in the high state During RESET on the
87C196KR C-step CLKOUT countinues to tog-
gle
OH2
1V with I
0 and MSEL0
15 mA
(A-step b-step)
ALE advanced 0 5 T
ALE pulse width remains 1 T
ALE advanced 0 5 T
ALE pulse width remains 1 T
Address advanced 0 5 T
OH
RAM
e b
e
e
0 Timings are altered by
6 mA C-step devices meet
OH2
OVERWRITE
1 in the CCB1 register
e
V
OSC
OSC
CC
OSC
OSC
OSC
b
OH2
1V with I
OSC
OSC
(A-step
e
V
the
OH
CC
e
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