an87c196kt Intel Corporation, an87c196kt Datasheet - Page 4

• Manufacturer Part Number: an87c196kt
• Description: Advanced 16-bit Chmos Microcontroller
• Manufacturer: Intel Corporation

87C196KT 87C196KS
PIN DESCRIPTIONS
4
V
V
V
V
ANGND
XTAL1
XTAL2
P2 7 CLKOUT
RESET
P5 7 BUSWIDTH
NMI
P5 1 INST
EA
P5 0 ALE ADV
P5 3 RD
P5 2 WR WRL
CC
SS
REF
PP
Symbol
V
SSI
V
SSI
Main supply voltage (
Digital circuit ground (0V) There are three V
Reference for the A D converter (
portion of the A D converter and the logic used to read Port 0 Must be connected for
A D and Port 0 to function
Programming voltage for the EPROM parts It should be
is also the timing pin for the return from powerdown circuit Connect this pin with a
1 mF capacitor to V
may be tied to V
Reference ground for the A D converter Must be held at nominally the same
potential as V
Input of the oscillator inverter and the internal clock generator
Output of the oscillator inverter
Output of the internal clock generator The frequency is
has a 50% duty cycle Also LSIO pin
Reset input to the chip Input low for at least 16 state times will reset the chip The
subsequent low to high transition resynchronizes CLKOUT and commences a 10-
state time sequence in which the PSW is cleared bytes are read from 2018H and
201AH loading the CCBs and a jump to location 2080H is executed Input high for
normal operation RESET has an internal pullup
Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin
dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’ and
CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’ all
bus cycles are 16-bit CCR bit 1
pin when not used as BUSWIDTH
A positive transition causes a non maskable interrupt vector through memory location
203EH
Output high during an external memory read indicates the read is an instruction fetch
INST is valid throughout the bus cycle INST is active only during external memory
fetches during internal EPROM fetches INST is held low Also LSIO when not INST
Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 2000H through 9FFFH to be directed to on-chip EPROM ROM
EA equal to a low causes accesses to these locations to be directed to off-chip
memory EA
latched at reset
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a latch to demultiplex the address from the address data bus When the pin is
ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip
select for external memory ALE ADV is active only during external memory
accesses Also LSIO when not used as ALE
Read signal output to external memory RD is active only during external memory
reads or LSIO when not used as RD
Write and Write Low output to external memory as selected by the CCR WR will go
low for every external write while WRL will go low only for external writes where an
even byte is being written WR WRL is active during external memory writes Also an
LSIO pin when not used as WR WRL
e a
SS
CC
12 5V causes execution to begin in the Programming Mode EA is
SS
a
and a 1 MX resistor to V
5V)
e
Name and Function
a
‘‘0’’ and CCR1 bit 2
5V) V
REF
SS
CC
is also the supply voltage to the analog
pins all of which MUST be connected
If this function is not used V
e
a
‘‘0’’ is illegal Also an LSIO
12 5V for programming It
the oscillator frequency It
PP
4