w77e58 Winbond Electronics Corp America, w77e58 Datasheet - Page 62

• Manufacturer Part Number: w77e58
• Description: 8 Bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

The main use of the Watchdog timer is as a system monitor. This is important in real-time control
applications. In case of some power glitches or electro-magnetic interference, the processor may
begin to execute errant code. If this is left unchecked the entire system may crash. Using the
watchdog timer interrupt during software development will allow the user to select ideal watchdog
reset locations. The code is first written without the watchdog interrupt or reset. Then the watchdog
interrupt is enabled to identify code locations where interrupt occurs. The user can now insert
instructions to reset the watchdog timer which will allow the code to run without any watchdog timer
interrupts. Now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. If
any errant code is executed now, then the reset watchdog timer instructions will not be executed at
the required instants and watchdog reset will occur.
The watchdog time-out selection will result in different time-out values depending on the clock speed.
The reset, when enabled, will occur 512 clocks after the time-out has occurred.
Table 9. Time-out values for the Watchdog timer
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into
a known state.
The control bits that support the Watchdog timer are discussed below.
WATCHDOG CONTROL
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog
WD1
0
0
1
1
the watchdog timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur
(if the global interrupt enable is set and other interrupt requirements are met). Software or any
reset can clear this bit.
This bit is useful for determined the cause of a reset. Software must read it, and clear it
manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by
the watchdog timer.
will leave the timer running.
timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but
WD0
0
1
0
1
Watchdog
Interval
2
2
2
2
17
20
23
26
Number of
Clocks
131072
1048576
8388608
67108864
- 62 -
Time
@ 1.8432 MHz
36408.88 mS
4551.11 mS
568.89 mS
71.11 mS
Preliminary W77E58
Time
@ 10 MHz
6710.89 mS
104.86 mS
838.86 mS
13.11 mS
Time
@ 25 MHz
2684.35 mS
335.54 mS
41.94 mS
5.24 mS