sx20ac Parallax, Inc., sx20ac Datasheet - Page 12

• Manufacturer Part Number: sx20ac
• Description: Configurable Communications Controllers With Ee/flash Program Memory, In-system Programming Capability And On-chip Debug
• Manufacturer: Parallax, Inc.

Parallax SX20AC/SX28AC
PLP_A, PLP_B, and PLP_C: Pullup Enable Registers
(MODE=0Eh)
Each register bit determines whether an internal pullup
resistor is connected to the pin. Set the bit to 1 to
disconnect the pullup resistor or clear the bit to 0 to
connect the pullup resistor.
LVL_A, LVL_B, and LVL_C: Input Level Registers
(MODE=0Dh)
Each register bit determines the voltage levels sensed on
the input port, either TTL or CMOS, when the Schmitt
trigger option is disabled. Program each bit according to
the type of device that is driving the port input pin. Set the
bit to 1 for TTL or clear the bit to 0 for CMOS.
ST_B and ST_C: Schmitt Trigger Enable Registers
(MODE=0Ch)
Each register bit determines whether the port input pin
operates with a Schmitt trigger. Set the bit to 1 to disable
Schmitt trigger operation and sense either TTL or CMOS
voltage levels; or clear the bit to 0 to enable Schmitt
trigger operation.
WKEN_B: Wakeup Enable Register (MODE=0Bh)
Each register bit enables or disables the Multi-Input
Wakeup/Interrupt (MIWU) function for the corresponding
Port B input pin. Clear the bit to 0 to enable MIWU
operation or set the bit to 1 to disable MIWU operation.
For more information on using the Multi-Input
Wakeup/Interrupt function, see Section 7.1.
WKED_B: Wakeup Edge Register (MODE=0Ah)
Each register bit selects the edge sensitivity of the Port B
input pin for MIWU operation. Clear the bit to 0 to sense
rising (low-to-high) edges. Set the bit to 1 to sense falling
(high-to-low) edges.
© Parallax Inc.
Page 12 of 51
(MODE=09h)
When you access the WKPND_B register using
“mov !rx,W”, the CPU does an exchange between the
contents of W and WKPND_B. This feature lets you read
the WKPND_B register contents while clearing the
Wakeup Pending bits simultaneously. Each bit indicates
the status of the corresponding MIWU pin. A bit set to 1
indicates that a valid edge has occurred on the
corresponding MIWU pin, triggering a wakeup or
interrupt. A bit set to 0 indicates that no valid edge has
occurred on the MIWU pin.
CMP_B: Comparator Register (MODE=08h)
When you access the CMP_B register using MOV
!RB,W, the CPU does an exchange between the contents
of W and CMP_B. This feature lets you read the CMP_B
register contents. Clear bit 7 to enable operation of the
comparator. Clear bit 6 to place the comparator result on
the RB0 pin. Bit 0 is a result bit that is set to 1 when the
voltage on RB2 is greater than RB1, or cleared to 0
otherwise. (For more information using the comparator,
see Section 11.0.)
3.2.3.
Upon reset, all the port control registers are initialized to
FFh. Thus, each pin is configured to operate as a high
impedance input that senses TTL voltage levels, with no
internal pullup resistor connected. The MODE register is
initialized to 0Fh, which allows immediate access to the
data direction registers using the “mov !rx,W” instruction.
WKPND_B: Wakeup Pending Bit Register
Port Configuration Upon Reset
Rev 1.6 11/20/2006
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