sx20ac Parallax, Inc., sx20ac Datasheet - Page 14

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sx20ac

Manufacturer Part Number
sx20ac
Description
Configurable Communications Controllers With Ee/flash Program Memory, In-system Programming Capability And On-chip Debug
Manufacturer
Parallax, Inc.
Datasheet

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Parallax SX20AC/SX28AC
4.3.
Bit 7
When the OPTIONX bit in the FUSE word is cleared, bits
7 and 6 of the OPTION register function as described
below.
When the OPTIONX bit is set, bits 7 and 6 of the
OPTION register read as ‘1’s.
RTW
RTE_IE RTCC edge interrupt enable:
RTS
© Parallax Inc.
RTW
RTW_IE
OPTION Register
RTCC/W register selection:
0 = Register 01h addresses W
1 = Register 01h addresses RTCC
0 = RTCC roll-over interrupt is enabled
1 = RTCC roll-over interrupt is disabled
RTCC increment select:
0= RTCC increments on internal instruction
cycle
1 = RTCC increments upon transition on RTCC
pin
RTS
RTE_ES
PSA
PS2
PS1
Bit 0
PS0
Page 14 of 51
RTE_ES RTCC edge select:
PSA
PS2-PS0 : Prescaler divider (see table below)
Upon reset, all bits in the OPTION register are set to 1.
PS2, PS1, PS0
07h111
000
001
010
011
100
101
110
0 = RTCC increments on low-to-high transitions
1 = RTCC increments on high-to-low transitions
Prescaler Assignment:
0 = Prescaler is assigned to RTCC, with divide
rate determined by PS0-PS2 bits
1 = Prescaler is assigned to WDT, and divide
rate on RTCC is 1:1
Table 4-2:
RTCC Divide
Prescaler Divider Ratios
1:128
1:256
Rate
1:16
1:32
1:64
1:2
1:4
1:8
Watchdog Timer
Rev 1.6 11/20/2006
Divide Rate
www.parallax.com
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8

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