tl0324s Newhaven Display International, Inc, tl0324s Datasheet - Page 12

• Manufacturer Part Number: tl0324s
• Description: 65com / 132seg Driver & Controller For Stn Lcd
• Manufacturer: Newhaven Display International, Inc

This circuit is for providing a page address to DDRAM shown in figure 6-6.
The 4-bit page address register changed by only the “Set page” instruction.
Page address 8 (DB3, DB2, DB1, DB0 = 1, 0, 0, 0) is a special RAM area for the icons and display data DB0
is only valid.
When Page Address is above 8, it is impossible to access to on-chip RAM.
5-2. DISPLAY DATA RAM (DDRAM)
a.
The DDRAM stores pixel data for the LCD.
It has 65-row (8 page x 8 bit + 1) by 132-column addressable array.
Each pixel can be selected by specifying the page and the column address.
The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read
from or written to the 8 lines of each page directly through DB7 to DB0.
The display data of DB0 to DB7 from the MPU correspond to the LCD common direction as shown in
Figure 5-4.
The MPU can read from and write to DDRAM through the I/O buffer, which is independent operation from
signal reading for the LCD driver.
This independent operation makes it possible that the MPU writes the data into the DDRAM at the same
time as data is being displayed without causing the LCD flicker.
b. Page address circuit
TOMATO LSI Inc.
DDRAM
TL0324S
DB0
DB1
DB2
DB3
DB4
0
1
1
0
1
Display data RAM
1
0
1
0
1
1
0
1
1
0
……
……
……
……
……
Figure 5-4. RAM-to-LCD data transfer
0
1
0
1
0
12
65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD
COM0
COM1
COM2
COM3
COM4
LCD display
……
……
……
……
……
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