x40031v14z-bt1 Intersil Corporation, x40031v14z-bt1 Datasheet - Page 10

• Manufacturer Part Number: x40031v14z-bt1
• Description: Triple Voltage Monitor With Integrated Cpu Supervisor
• Manufacturer: Intersil Corporation

Figure 6. V
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
TRIPX
Old V
New V
X
Set/Reset Sequence (X = 1, 2, 3)
applied + | Error |
X
applied =
10
Error < MDE
NO
–
X40030, X40031, X40034, X40035
No
V
Set V
Set Higher V
Apply V
> Desired V
TRIPX
V
TRIPX
Desired V
Output Switches?
Actual V
Present Value
X
Decrease V
Reset Sequence
= desired V
V
Desired
Execute
Execute
CC
Programming
DONE
TRIPX
and Voltage
TRIPX
X
TRIPX -
| Error | < | MDE |
TRIPX
<
Sequence
YES
YES
to V
X
TRIPX
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t
shown in the following table.
PURST
X
PUP1
0
0
1
1
time delay. The nominal power up times are
PUP0
Error > MDE
0
1
0
1
Old V
Execute Reset V
New V
X
Power on Reset Delay (
Sequence
applied - | Error |
+
Vx = V
Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error
X
applied =
Desired Value
200ms (factory setting)
CC
TRIPX
, VxMON
MDE
MDE
Error = Actual - Desired
400ms
800ms
50ms
+
–
Error Range
Acceptable
t
PURST
May 25, 2006
FN8114.1
)