x5163s8zt2 Intersil Corporation, x5163s8zt2 Datasheet - Page 7

• Manufacturer Part Number: x5163s8zt2
• Description: Cpu Supervisor With 16kbit Spi Eeprom
• Manufacturer: Intersil Corporation

SPI Serial Memory
The memory portion of the device is a CMOS Serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
INSTRUCTION NAME
WREN CMD
WEL
WRDI/RFLB
0
1
1
1
WRITE
WREN
WRSR
RDSR
READ
SFLB
STATUS REGISTER
WPEN
INSTRUCTION FORMAT*
X
X
1
0
7
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
0000 0110
DEVICE PIN
WP#
X
X
0
1
TABLE 2. BLOCK PROTECT MATRIX
TABLE 1. INSTRUCTION SET
™
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
Write Status Register (Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
cell,
PROTECTED BLOCK
X5163, X5165
Protected
Protected
Protected
Protected
BLOCK
Write Enable Latch
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
WPEN
7
UNPROTECTED BLOCK
FLB
6
OPERATION
Protected
Writable
Writable
Writable
BLOCK
WD1
5
WD0
4
BL1
WPEN, BL0, BL1, WD0,
3
STATUS REGISTER
BL0
Protected
Protected
2
Writable
Writable
WD1
WEL
1
June 1, 2006
FN8128.3
WIP
0