m40z111 STMicroelectronics, m40z111 Datasheet

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m40z111

Manufacturer Part Number
m40z111
Description
5v Or 3v Nvram Supervisor For Up To Two Lpsrams
Manufacturer
STMicroelectronics
Datasheet

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Features
November 2007
Convert low power SRAMs into NVRAMs
Precision power monitoring and power
switching circuitry
Automatic write-protection when V
tolerance
Choice of supply voltages and
power-fail deselect voltages:
– M40Z111: V
– M40Z111W: V
Less than 15ns chip enable access
propagation delay (for 5.0v device)
Packaging includes a 28-lead SOIC and
SNAPHAT
SOIC package provides direct connection for a
SNAPHAT top which contains the battery
RoHS compliant
– Lead-free second level interconnect
THS = V
THS = V
THS = V
V
THS = V
CC
= 2.7 to 3.3V
®
OUT
OUT
SS
SS
top (to be ordered separately)
; 4.5
; 2.8
CC
; 4.2
; 2.5
CC
= 4.5 to 5.5V
5V or 3V NVRAM supervisor for up to two LPSRAMs
= 3.0 to 3.6V
V
V
V
V
PFD
PFD
PFD
PFD
4.75V
3.0V
4.5V
2.7V
CC
is out-of-
Rev 4
28
SNAPHAT (SH)
SOH28 (MH)
battery
1
M40Z111W
M40Z111
www.st.com
1/21
1

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m40z111 Summary of contents

Page 1

... NVRAM supervisor for up to two LPSRAMs Features ■ Convert low power SRAMs into NVRAMs ■ Precision power monitoring and power switching circuitry ■ Automatic write-protection when V tolerance ■ Choice of supply voltages and power-fail deselect voltages: – M40Z111 4.5 to 5.5V CC THS = PFD THS = V ; 4.2 V OUT PFD – ...

Page 2

Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... Description The M40Z111/W NVRAM supervisor is a self-contained device which converts a standard low-power SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the V condition. When an invalid V CC inactive to write-protect the stored data in the SRAM. During a power failure, the SRAM is switched from the V ® ...

Page 6

... Conditioned chip enable output Supply voltage output Supply voltage Ground Not connected internally V OUT M40Z111 22 M40Z111W THS AI02239B ...

Page 7

... Figure 3. Hardware hookup 3.0, 3. 1N5817 or 0.1 F MBR5120T3 Thereshold OUT 0.1 F M40Z111/W E CON E THS CMOS SRAM x16 AI02394 7/21 ...

Page 8

... SUPERVISOR. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and SRAMs to be “Don't Care” once V guarantee data retention down to V sufficient to meet the system needs with the chip enable propagation delays included ...

Page 9

The available battery capacity for the SNAPHAT current to determine the amount of data retention available (see more information on Battery Storage Life refer to the Application Note AN1012. Figure 4. Power down timing PFD (max) V ...

Page 10

... V rise time PFD CC (min) V rise time PFD CC M40Z111 M40Z111W M40Z111 M40Z111W M40Z111 M40Z111W = –40 to 85° (min) fall time of less than t may result in deselection/write protection not occurring F passes V (min). PFD may cause corruption of RAM data. FB bus. These transients can be reduced if ...

Page 11

Figure 6. Supply voltage protection 0.1 F DEVICE V SS AI00622 11/21 ...

Page 12

... Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 12/21 Parameter Grade 6 ® SNAPHAT off) CC SOIC M40Z111 M40Z111W Value Unit – °C – °C –55 to 125 °C 260 °C –0 +0.3 ...

Page 13

... M40Z111W. Table 5. Capacitance Symbol C Input capacitance IN (3) C Output capacitance OUT 1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only, not 100% tested 25° 1MHz. 3. Outputs deselected conditions. Designers should check that the operating conditions ) L 645 DEVICE UNDER TEST ...

Page 14

... OUT BAT 2.0 3.0 2 –0 –2.0mA 2 –1.0µA 2.0 2.9 OUT2 I = 4.0mA 4.50 4.60 4.20 4.35 3.0 = –40 to 85° 4.5 to 5.5V or 2.7 to 3.6V (except where noted M40Z111W Max Min Typ Max 150 150 ±1 ±1 ±1 ±1 160 100 100 65 100 3.5 2.0 3.0 3 0.3 2.0 0.3 0.8 –0.3 0.8 2 ...

Page 15

Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...

Page 16

Table 7. SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data Symbol Typ 1. 16/21 mm Min Max Typ 3.05 0.05 0.36 2.34 2.69 ...

Page 17

Figure 9. 4-pin SNAPHAT housing for 48mAh battery, package outline Note: Drawing is not to scale. Table 8. 4-pin SNAPHAT housing for 48mAh battery, package mechanical data Symbol Typ ...

Page 18

Figure 10. 4-pin SNAPHAT housing for 120mAh battery, package outline Note: Drawing is not to scale. Table 9. 4-pin SNAPHAT housing for 120mAh battery, package mechanical data Symbol Typ 18/21 ...

Page 19

Part numbering Table 10. Ordering information scheme Example: Device type M40Z Supply voltage and write protect voltage 111 = V = 4.5 to 5.5V THS = V = 4.5 SS THS = V = 4.2 OUT 111W ...

Page 20

Revision history Table 12. Document revision history Date Revision Sep-2000 14-Sep-2001 13-May-2002 12-Nov-2007 20/21 1 First Draft Issue Reformatted, TOC added, changed DC Characteristics changed battery, ind. temperature information 2 Figure 9, 10); Corrected SOIC label (Figure 3) 3 ...

Page 21

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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