x5645s14i-4.5a Intersil Corporation, x5645s14i-4.5a Datasheet - Page 8

• Manufacturer Part Number: x5645s14i-4.5a
• Description: Cpu Supervisor With 64kbit Spi Eeprom
• Manufacturer: Intersil Corporation

While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
– SO pin is high impedance.
Figure 6. Read Status Register Sequence
Figure 7. Write Enable Latch Sequence
an active state and receive an instruction.
SCK
CS
SO
SI
8
High Impedance
SCK
CS
SO
SI
0
1
Instruction
High Impedance
2
0
3
1
4
2
X5643, X5645
5
3
6
4
7
MSB
5
8
7
– The write enable latch is reset.
– The flag bit is reset.
– Reset signal is active for t
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
– CS must come HIGH at the proper clock count in
6
enable latch.
order to start a nonvolatile write cycle.
9
6
7
10 11 12 13 14
5
Data Out
4
3
2
1
0
PURST
.
July 18, 2005
FN8135.1