x40626 Intersil Corporation, x40626 Datasheet - Page 12

• Manufacturer Part Number: x40626
• Description: Dual Voltage Cpu Supervisor With 64k Serial Eeprom
• Manufacturer: Intersil Corporation

X40626
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
Figure 13. Random Address Read Sequence
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a stop
is issued instead of the second start shown in Figure
13. The device goes into standby mode after the stop
and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
REV 1.1.15 2/11/04
Signals from
Signals from
the Master
SDA Bus
the Slave
S
A
R
T
T
S
1 0 1 0
Address
Slave
0
S
1
S
0
0
A
C
K
Word Address
Byte 1
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A
C
K
Word Address
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
cating it requires additional data. The device continues
to output data for each acknowledge received. The
master terminates the read operation by not respond-
ing with an acknowledge and then issuing a stop condi-
tion.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000H and the device continues
to output data for each acknowledge received. Refer to
Figure 14 for the acknowledge and data transfer
sequence.
Byte 0
A
C
K
S
R
S
T
A
T
1 0 1 0
Characteristics subject to change without notice.
Address
Slave
0
S
1
S
0
1
A
C
K
Data
O
P
S
T
P
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