lf3320 LOGIC Devices Incorporated, lf3320 Datasheet
lf3320
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lf3320 Summary of contents
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... Registers) allow interleaved data to be fed directly into the device and fil- tered without separating the data into individual data streams. The LF3320 can handle a maximum of sixteen data sets interleaved together. The I/D Registers and on-chip accu- mulators facilitate using decimation to increase the number of filter taps. ...
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... DEVICES INCORPORATED F 1. LF3320 F IGURE UNCTIONAL 11-0 OUT DATA RSLB REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1- DATA 1-16 REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 CENA B D LOCK IAGRAM 2-2 LF3320 Horizontal Digital Image Filter LDB PAUSEB 11-0 CFB LDA PAUSEA CFA 11-0 Video Imaging Products 6/22/2007–LDS.3320-R ...
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... Reverse Cascade Input 11-0 In Single Filter Mode, RIN is the 11-0 12-bit reverse cascade input port. This port is connected to ROUT of 11-0 another LF3320. In Dual Filter Mode, RIN can be the 12-bit input port to 11-0 Filter B. Data is latched on the rising edge of CLK. CFA — Coefficient A Input 11-0 CFA ...
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... ROUT on one device should 11-0 be connected to RIN of another 11-0 LF3320. In Dual Filter Mode, ROUT is a 4-bit registered output port for the upper four bits of the 16-bit Filter B output. In this mode, ROUT 11-4 disabled. Controls LDA — Coefficient A Load When LDA is LOW, data on CFA ...
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... REGISTERS FILTER A R.S.L. CIRCUIT 16 DOUT 15-0 2-5 LF3320 Horizontal Digital Image Filter A LF Interface loading sequence is TM halted until PAUSEA is returned to a LOW state. This effectively allows the user to load coefficients and con- trol registers at a slower rate than the master clock (see the LF Interface section for a full discussion). PAUSEB — ...
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... Filter B. COUT11-0 is the twelve least significant bits and ROUT3-0 is the four most significant bits of the 16-bit Filter B output. Matrix-vector Multiply Mode In this mode, the LF3320 can be con- 11-0 figured to multiply a square matrix of maximum size 16), multi- plied by a matrix-vector of maximum size [8,1] or [16,1] ...
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... Configuration Register 5 will con- figure the device for single filter mode, [16x16][16x1] matrix-vector multiplication. Some functions of the LF3320 must be disabled when configured for matrix-vector multiplication. This will apply to both the single filter mode and the dual filter mode; these func- tions are data reversal and interleave/ decimation ...
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... Configuration Registers, the coef- ficient sets, and the data values have been loaded. The corresponding timing diagram loading sequence for the coefficient banks and Configuration/Control registers are included in the LF3320 data sheets (Figure 11 and Figure 12 respectively). 2-8 Horizontal Digital Image Filter 14 15 ...
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... DEVICES INCORPORATED Coefficient Mode. However, there are some special considerations when this mode is desired. The LF3320 must be configured for single filter mode only, for a maximum (8x8) matrix. The user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (see Table 7) ...
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... With no decimation, the maximum number of filter taps is sixteen. When decimat- ing by N, the number of filter taps becomes 16N because there are N–1 clock cycles when the filter’s output is Video Imaging Products LF3320 COEF 7 2 COEF 6 ...
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... I/D Registers in which data flows from left to right in the block diagram in Figure 1. The reverse data path contains the I/D Registers in which 2-11 LF3320 Horizontal Digital Image Filter data flows from right to left. In Single or Dual Filter Modes, data is fed from the forward data path to the reverse data path as follows ...
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... LF3320s are cascaded together LF3320 is the last in the cascade chain, Bit 0 of Configuration Register 5 should be set to a “0”. This will cause the data from the end of the forward ...
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... COUT and ROUT output registers. The data routing circuitry is required to correctly align data in the forward and reverse data paths as data passes from one LF3320 to another. The COUT and ROUT registers are loaded with data which is two clock cycles behind the current output of the I/D Register just before the ROUT or COUT register ...
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... Output Limiting An output limiting function is pro- vided for the overall filter, Filter A, and Filter B outputs. The Filter A lim- 2-14 LF3320 Horizontal Digital Image Filter iting circuitry is used to limit the over- all filter output (Single Filter Mode) and the Filter A output (Dual Filter Mode) ...
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... LF Interface section. TM Configuration and Control Registers The configuration registers determine how the LF3320 operates. Tables 2 through 7 show the formats of the six configuration registers. There are three types of control registers: round, select, and limit. There are sixteen round registers for Filter A and six- teen for Filter B ...
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... Table 19 shows an example of loading data into Filter B limit register 7. Data value 3B60H is loaded as the COEFFICIENT SET 3 W2 COEF ADDR COEF COEF LIMIT REGISTER W4 ADDR DATA DATA DATA DATA MPLEMENTATION COEF 7 Video Imaging Products 6/22/2007–LDS.3320-R LF3320 W3 W1 ...
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... Filter B Select Registers Filter A Round Registers Filter B Round Registers Filter A Limit Registers Filter B Limit Registers PAUSE I MPLEMENTATION SELECT REGISTER DATA 2 1 MPLEMENTATION DATA DATA 3 4 Video Imaging Products 6/22/2007–LDS.3320-R LF3320 remain dis The Con- D ECODE W2 W1 ...
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... DATA DATA 11 EGIS ABLE LTR IMIT REGISTER ADDRESS (HEX) 0 C00 1 C01 14 C0E 15 C0F 14 EGIS ABLE LTR IMIT REGISTER ADDRESS (HEX) 0 E00 1 E01 14 E0E 15 E0F will TM Video Imaging Products 6/22/2007–LDS.3320-R LF3320 EGIS R - EGIS ...
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... CFA/B CFA/B CFA/B CFA/B CFA Video Imaging Products LF3320 CFA CFA CFA ...
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... Ground ≤ V ≤ V (Note 12 Ground ≤ V ≤ V (Note 12) OUT CC (Notes 5, 6) (Note 25° MHz 25° MHz A 2-20 LF3320 Horizontal Digital Image Filter Voltage Supply 3.00V ≤ V ≤ 3.60V CC 3.00V ≤ V ≤ 3.60V CC Min Typ Max 2.4 0.4 2.0 5.5 0.0 0.8 ±10 ± ...
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... I PWL t PWH DIN/RIN t N+1 CYC CAA/CAB N+1 t ENA t DIS HIGH IMPEDANCE t ENA t DIS HIGH IMPEDANCE 2-21 LF3320 Horizontal Digital Image Filter LF3320– Min Max Min Max Min ...
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... Min Max NTERFACE PWL 2-22 Horizontal Digital Image Filter LF3320– Min Max Min Max 6 5 Video Imaging Products LF3320 9 Min Max 5 6/22/2007–LDS.3320-R ...
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... Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst- 2-23 LF3320 Horizontal Digital Image Filter case operation of any device always provides data within that time. 11. For the t test, the transition is ENA measured to the 1 ...
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... LF3320QC15 (GREEN LF3320QC12 12 ns LF3320QC12G (GREEN LF3320QC9 LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete ...