lf3324 LOGIC Devices Incorporated, lf3324 Datasheet
lf3324
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lf3324 Summary of contents
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... Write and Read Pointers may be independently jumped to arbitrary address locations • Write or Read Pointers can be manipulated in real- time based on external 24bit address NOTE: This Preliminary Datasheet references LF3324BGC Engineering Samples with an E marking under the part designation. Applications SD/HDTV Video Stream Buffer ...
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... DEVICES INCORPORATED LF3324 Overview The LF3324 Mbit memory device that handles 8, 10, or 12bit data. The input data port may be clocked asynchronously to the output ports. Since reads are non-destructive, a given data value, once written into the memory core, may be read as many times as desired. A user requiring more storage can cascade up to eight LF3324s into a larger array ...
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... SCL 3 24Mbit Frame Buffer / FIFO Preliminary Datasheet RCLK READ READ READ ADDRESS RSET CONTROL A CONTROL RCLR OE 12 Q[11:0] PF FLAG COLLIDE GENERATOR PE RCLK READ READ ADDRESS RSET CONTROL RCLR OE 12 Q[11:0] 24 RADDRSEL WADDRSEL 24 ADDR[23:0] Video Imaging Product June 8, 2007 LDS.3324 G LF3324 REN REN ...
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... The input (write) and output (read) clocks need not be synchronous with one another, although the memory core may fill or empty if they differ in average frequency. After it “fills,” the LF3324 continues writing and the oldest data gets written over. If the memory core “empties” (and neither the read nor write pointer have been set or cleared during run-time) the read pointer stops incrementing, and the device re-reads the last written sample until more data is written ...
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... ROW_LENGTH to 1716 decimal = 6B4 hex. Offset circuitry within the LF3324 permits the user to cascade several chips in parallel and to use them collectively as a single large memory with a seamless address space. Data are read out sequentially by rising edges of RCLK, under the control of REN (read enable), RSET (read pointer force to constant), and RCLR (read pointer clear to 0) ...
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... Multiple devices can be cascaded to deepen the address space. For every device cascaded more of the 24bit address space is used. Internally, the LF3324 has a 24bit address space. The LF3324 was designed to be cascaded in parallel. That is, the inputs of each device are tied together. The input data word (the data word placed on the D input port common for all devices. Similarly, the outputs of all devices are tied together. Each device’ ...
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... In contrast, during a read operation, if there is no acknowledgement back from the master device, the LF3324 interprets this were the end of the data transmission, and leaves SDA high, allowing the master to generate its stop signal. ...
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... R/W bit this time HIGH signifying a read and wait for an acknowledge. The user must write to the LF3324 to select the appropriate initial target register. Otherwise the starting position of the read is uncertain. Once the LF3324 acknowledges, the next byte of data on SDA is the contents of the addressed register sent from the device. If the master acknowledges, the LF3324 will send the next higher register’ ...
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... CDLY Write Cycle - Normal Mode PCEx t CSU PWE t CSU PRE t CSU Read Cycle - PRE held low t CSU t CDLY Write Cycle - PRE held low t CSU 9 LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet t CSPW CSPW t t CSU CHD t CSPW CSPW t t CSU ...
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... All pins must be connected. Clocks WCLK - Write Clock Data present on D11-0 is written into the LF3324 on the rising edge of WCLK when WEN was LOW for the previous rising edge of WCLK. RCLK - Read Clock In data is read from the LF3324 and presented on the output port (Q11-0) after a rising edge of RCLK while REN and OE are LOW ...
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... WIEN is used to enable/disable writing into the memory core. A LOW on WIEN enables writing, while a HIGH on WIEN disables writing. The internal write address pointer is incremented by WEN regardless of the WIEN level. If disabling of WIEN is never desired, tie WIEN LOW. LOGIC Devices Incorporated 24Mbit Frame Buffer / FIFO Preliminary Datasheet 11 LF3324 Video Imaging Product June 8, 2007 LDS.3324 G ...
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... Therefore when desiring not to read a sample, REN must be brought high the cycle before. PROGRAM - Serial/Parallel Interface Selector When the user wishes to use the serial microprocessor to configure the LF3324, the PROGRAM pin must be set LOW. If the user wishes to use the parallel interface, PROGRAM must be set HIGH. ...
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... TDO is the output data pin when using JTAG. TRSTB - JTAG reset TRSTB is used to reset all the registers and state machine fount the the JTAG module. LOGIC Devices Incorporated 24Mbit Frame Buffer / FIFO Preliminary Datasheet 13 LF3324 Video Imaging Product June 8, 2007 LDS.3324 G ...
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... Frame Buffer / FIFO (0000: 24-bit linear map; see reg 7) (00000000: 24-bit linear map; see reg 6) (00000000: default = 0; see reg 9, a) (00000000: default = 0; see reg 8, a) (00000000: default = 0; see reg 8, 9) (00000000) (00000000) (00000000) 14 LF3324 Preliminary Datasheet Video Imaging Product June 8, 2007 LDS.3324 G ...
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... RCLR is falling edge triggered) Reserved - set to 0 Reserved - set to 0 (0: WSET is falling edge triggered) (0: WCLR is falling edge triggered) RESERVED (00: PE, PF are part-empty, -full) (0000: lowest-address chip in cascade sequence) (0000: single chip - no cascade of multiple chips) 15 LF3324 Preliminary Datasheet Video Imaging Product June 8, 2007 LDS.3324 G ...
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... LOGIC Devices Incorporated Input Port 8 bits D[11:4] 10 bits D[11:2] (default) 12 bits D[11:0] ignores the internal RSET that occurs following the MARK obeys the internal RSET according to the MARK 16 LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet Output Port Q[11:4] (Q[3:0] tristated) Q[11:2] (Q[1:0] tristated) Q[11:0] Video Imaging Product June 8, 2007 LDS.3324 G ...
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... F-bit in EAV (field-based sync) force read pointer(s) to marked address(es) (default) force read pointer(s) as shown in following table: RADRSEL Read Pointer Equals: 1 ADDR[23:0] address 0 RADDR address 17 LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet Video Imaging Product June 8, 2007 LDS.3324 G ...
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... The corresponding pin continuously overrides the memory address counter as long held LOW. Memory address incrementing resumes when the pin is returned HIGH. Reserved 18 LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet Video Imaging Product June 8, 2007 LDS.3324 G ...
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... Register C[7:4] = BASE_ADDR[3:0] - position of chip in cascade series; 0000 = lowest; BASE_ADDR[3:0] must not exceed CASCADE[3:0]** 0000: 0001: .... 0111: ** Note: There are two cascaded die per LF3324. Die 0 is chip die 2 is chip Register C[3:0] = CASCADE[3:0] - number of chips in a system with concatenated address spaces*. 0001: 0011: .... ...
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... DEVICES INCORPORATED Reserved Configuration Registers Instruction registers D hex and above are reserved for test purposes only. LOGIC Devices Incorporated 24Mbit Frame Buffer / FIFO Preliminary Datasheet 20 LF3324 Video Imaging Product June 8, 2007 LDS.3324 G ...
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... V (Note 12) OUT CC (Note 5,6) (Note 25° MHz 25° MHz A 21 LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet –65°C to +150°C –0. 2.0V –0. 4.0V –0. 3. > 400 mA Supply Voltage 1.71V < Vcc < 1.89V 3.00V < Vcc < 3.60V Min Typ ...
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... Parallel Interface Control Output Delay Parallel Interface Control Tristate Delay LOGIC Devices Incorporated 24Mbit Frame Buffer / FIFO Preliminary Datasheet - Min LF3324 LF3324BGC Max Max Min Video Imaging Product June 8, 2007 LDS.3324 G ...
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... NOTE: REN should be brought LOW 2 rising edges of RCLK prior to expecting valid data on Q LOGIC Devices Incorporated t t WES WEH (n+1) (n+3) (n+ WES WEH (n+1) (n+3) (n+4) t RES t REH (n) (n+ LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet (n+5) data not data not written written (n+7) (n+5) (n+ (n+2) (n+3) Video Imaging Product June 8, 2007 LDS.3324 G ...
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... Address "A" on ADDR) for the contents of location dumped onto Q LOGIC Devices Incorporated RWH RWS (0) (1) 2 .... (n+1) (n+ 23–0 (n-1) (n) (n+13) 24 24Mbit Frame Buffer / FIFO Preliminary Datasheet RWH RWS (2) (A) (A+ (n+8) ( (A) (A+1) Video Imaging Product LF3324 (1) June 8, 2007 LDS.3324 G ...
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... RSET can be brought LOW (edge "7") 7 rising edges of RCLK after the LOAD transition, jumping the read pointer to the address programmed into the RADDR register. LOGIC Devices Incorporated 23-0 t RWS (A) (A+1) OPMODE[2:0]=001 t DIS RWH t t RWS RWH 25 24Mbit Frame Buffer / FIFO Preliminary Datasheet (A+2) (A+3) (A+4) t ENA HIGH IMPEDANCE RWH t t RWS RWH Video Imaging Product June 8, 2007 LDS.3324 G LF3324 ...
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... Ground and VCC supply planes must be brought directly to the device leads. c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to maintain required input levels relative to the device ground pin. LOGIC Devices Incorporated 2 26 LF3324 24Mbit Frame Buffer / FIFO Preliminary Datasheet Video Imaging Product June 8, 2007 LDS.3324 G ...
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... IGURE HRESHOLD EVELS t t ENA DIS OE 1 Measured V with I = –10mA and I = 10mA Measured V with I = –10mA and I = 10mA Video Imaging Product June 8, 2007 LDS.3324 G LF3324 3.0V Vth Vth ...
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... GND ADDR ADDR INT 3 INT PDATA ADDR ADDR VCCI ADDR VCCO TCK ADDR ADDR ADDR PDATA TMS TDI GNDO VCC 0 INT P PDATA TRST_b TDO VCCO GND 3 1 INT 1.00 REF Video Imaging Product LF3324 June 8, 2007 LDS.3324 G ...
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... DEVICES INCORPORATED Document History Page LF3324 24M OCUMENT ITLE Rev. ECN NO. Issue Date A 03/08/05 B 03/28/05 C 04/07/05 D 08/18/05 E 09/14/05 F 07/7/06 G 06/08/07 LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete ...