W256 Cypress Semiconductor Corp., W256 Datasheet - Page 3

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W256

Manufacturer Part Number
W256
Description
12 Output Buffer For 2 DDR And 3 Sdram Dimms
Manufacturer
Cypress Semiconductor Corp.
Datasheet

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Serial Configuration Map
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 1
Bit 3 27, 26 DDR5T_SDRAM10,
Bit 2 --
• The Serial bits will be read by the clock driver in the following
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the W256 is:
Bit
order:
A6
1
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Pin #
A5
1
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
FBOUT
DDR5C_SDRAM11
Reserved, drive to 0
A4
0
A3
1
Description
A2
0
Preliminary
A1
0
A0
1
0
0
0
1
1
1
Default
R/W
----
3
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit 1 23, 22 DDR4T_SDRAM8,
Bit 0 --
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
--
19, 18
12, 13
--
--
7, 8
--
3, 4
Pin #
DDR4C_SDRAM9
Reserved, drive to 0
Reserved, drive to 0
DDR3T_SDRAM6,
DDR3C_SDRAM7
DDR2T_SDRAM4,
DDR2C_SDRAM5
Reserved, drive to 0
Reserved, drive to 0
DDR1T_SDRAM2,
DDR1C_SDRAM3
Reserved, drive to 0
DDR0T_SDRAM0,
DDR0C_SDRAM1
Description
1
1
1
1
1
1
1
1
Default
W256
1
1

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