tc59lm818dmg TOSHIBA Semiconductor CORPORATION, tc59lm818dmg Datasheet - Page 46

no-image

tc59lm818dmg

Manufacturer Part Number
tc59lm818dmg
Description
288mbits Network Fcram2 ? 4,194,304-words ? 4 Banks ? 18-bits
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
tc59lm818dmg-33
Manufacturer:
TOSHIBA
Quantity:
15 405
Bank, Address
Bank, Address
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
AUTO-REFRESH TIMING (CL = 4, BL = 4)
Command
Command
(output)
(output)
(output)
(output)
CLK
CLK
CLK
CLK
CLK
DQ
DQ
QS
QS
WRA REF
I
RCD
Hi-Z
Hi-Z
Note: In case of CL = 4, I
Low
Bank,
Bank,
I
RDA
RDA
RCD
UA
UA
t
than Read / Write operation.
REFI
0
= 1 cycle
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh
command specified by t
t
= 1 cycle
REFI
t
is specified to avoid partly concentrated current of Refresh operation that is activated larger area
1
t
REFI
LAL
LAL
LA
LA
is average interval time in 8 Refresh cycles that is sampled randomly.
1
WRA REF
=
I
Total time of 8 Refresh cycle
RC
I
RC
2
= 5 cycles
I
RAS
= 5 cycles
I
REFC
CL = 4
RAS
t
2
= 4 cycles
CL = 4
DESL
DESL
= 4 cycles
REFI
3
must be meet 19 clock cycles.
8
WRA REF
must be satisfied.
8 Refresh cycle
4
t
3
I
WRA
WRA
RCD
I
RCD
5
=
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
t
= 1 cycle
1
= 1 cycle
+ t
REF
REF
2
6
+ t
3
+ t
4
t
7
8
+ t
7
I
I
REFC
REFC
WRA REF
5
+ t
TC59LM818DMG-33,-40
6
n − 1
= 19 cycles
= 19 cycles
+ t
DESL
DESL
7
+ t
t
8
Low
Hi-Z
Hi-Z
8
n
2005-10-19 46/57
WRA REF
n + 1
WRA
WRA
RDA
RDA
or
or
MRS or
MRS or
LAL or
LAL or
n + 2
REF
REF
Rev 1.4

Related parts for tc59lm818dmg