ak5702 AKM Semiconductor, Inc., ak5702 Datasheet - Page 50

• Manufacturer Part Number: ak5702
• Description: 4-channel Adc With Pll & Mic-amp
• Manufacturer: AKM Semiconductor, Inc.

(2) I
The AK5702 supports the fast-mode I
(2)-1. WRITE Operations
Figure 47 shows the data transfer sequence for the I
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 53). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0
(device address bit). This bit identifies the specific device on the bus. The hard-wired input pins (CAD1/0 pins) set these
device address bits (Figure 48). If the slave address matches that of the AK5702, the AK5702 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 54). A R/W bit value of “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5702. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 49). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 50). The AK5702 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 53).
The AK5702 can perform more than one byte write operation per sequence. After the receipt of the third byte the AK5702
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1CH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 55) except for the START and STOP
conditions.
MS0623-E-00
2
C-bus Control Mode (I2C pin = “H”)
SDA
S
T
A
R
T
S
Slave
Address
D7
0
0
R/W="0"
Figure 47. Data Transfer Sequence at the I
A
C
K
D6
0
(Those CAD1/0 should match with CAD1/0 pins)
0
Figure 50. Byte Structure after the second byte
Sub
Address(n)
2
C-bus (max: 400kHz).
A5
D5
1
Figure 49. The Second Byte
Figure 48. The First Byte
C
A
K
2
C-bus mode. All commands are preceded by a START condition. A
Data(n)
A4
D4
0
- 50 -
A
C
K
A3
D3
0
Data(n+1)
CAD1
2
A2
D2
C-Bus Mode
C
A
K
CAD0
A1
D1
A
C
K
Data(n+x)
R/W
A0
D0
C
A
K
S
T
O
P
P
[AK5702]
2007/06