73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 138

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

Revision History
138
Revision
1.0
1.1
1.2
Date
5/15/2007
11/7/2007
12/16/2008
Description
First publication.
On
protocols T=0, T=1” to “ISO-7816 UART for protocols T=0, T=1”.
In
In
references.
In
preferred location for the user’s preboot code, may not be page-erased by
either MPT or ICE. Page zero may only be erased with global flash erase.
Note that global flash erase erases XRAM whether the SECURE bit is set
or not.” to “Page zero of flash memory may not be page-erased by either
MPU or ICE. Page zero may only be erased with global flash erase. Note
that global flash erase erases XRAM whether the SECURE bit is set or
not.”
In
must be bound between a value of 1 to 7. The possible crystal or external
clock are shown in Table 12.“ to “Mcount is configured in the MCLKCtl
register must be bound between a value of 1 to 7. The possible crystal or
external clock frequencies for getting MCLK = 96MHz are shown in Table
11.”
In
and power applied to the VBUS input, the 73S1217F will go into either
standby mode or power “OFF” mode. If system power is provided by,
VBUS or the ON/OFF circuitry is in the “ON” state, the MPU core will
placed into standby mode.”
In the
using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”
In
description: “The signals of the emulator port have weak pull-ups. Adding
resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is
recommended. If necessary, adding 10KΩ pull-up resistors on E_TCLK
and E_RXTX and a 3KΩ on E_RST will help the emulator operate
normally if a problem arises.”
In
In the
an emergency deactivation of the internal smart card slot. See the
Fault Detect Function
Changed last sentence of the
prior to the FIFO and is stored in the receive FIFO,” to “TS is decoded
before being stored in the receive FIFO.”
In
In
SEC, TEST and PRES pins.
In
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
Table
Section
Section
Section
Section
Section
Section
Ordering
Table
Section
page
BRCON
VccCtl
1, removed NC, pin 44 row.
1, added more description to the VCC, VPC, VDD, SCL, SDA,
2, changed bullet from “ISO-7816 UART 9600 to 115kbps for
1.4, changed description to remove pre-boot and 32-cycle
1.4, changed the second bullet “Page zero of flash memory, the
1.7.1, changed “Mcount is configured in the MCLKCtl register
1.7.4, added “Depending on the state of the ON/OFF circuitry
1.7.15, removed the following from the emulator port
1.7.17.1, added 230000 to the baud rate selections in bullet 7.
1.3.2, changed “FLSH_ERASE” to “ERASE” and
Information, removed the leaded part numbers.
description, added “The VDDFLT bit (if enabled) will provide
description, changed “If BSEL = 1, the baud rate is derived
section for more detail.”
DETTS
bit description from “TS is decoded
VDD
Rev. 1.2