73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 46

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave
processors compare the received byte with their network address. If there is a match, the addressed
slave will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave the
SM20 or SM21 bit unaffected and ignore this message. After addressing the slave, the host will output
the rest of the message with the 9th bit set to 0, so no serial port receive interrupt will be generated in
unselected slaves.
Serial Interface Control Register (S1CON): 0x9B
The function of the serial port depends on the setting of the Serial Port Control Register S1CON.
Multiprocessor operation mode: The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0
or in Mode A of Serial Interface 1 can be used for multiprocessor communication. In this case, the slave
processors have bit SM20 in
46
S1CON.7
S1CON.6
S1CON.5
S1CON.4
S1CON.3
S1CON.2
S1CON.1
S1CON.0
Bit
MSB
SM
Symbol
SM21
REN1
RB81
TB81
SM
TI1
RI1
–
–
S0CON
Sets the UART operation mode.
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable
reception.
The 9th transmitted data bit in Mode A. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.).
In Mode B, if sm21 is 0, rb81 is the stop bit. Must be cleared by
software.
Transmit interrupt flag, set by hardware after completion of a serial
transfer. Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial
reception. Must be cleared by software.
SM
SM21
Table 39: The S1CON Register
0
1
or SM21 in
Mode
REN1
A
B
S1CON
TB81
Description
0x00
9-bit UART
8-bit UART
set to 1. When the master processor outputs
RB81
Function
Baud Rate
TI1
variable
variable
RI1
LSB
Rev. 1.2