78p2343jat Teridian Semiconductor Corporation, 78p2343jat Datasheet - Page 11

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78p2343jat

Manufacturer Part Number
78p2343jat
Description
3-port E3/ds3/sts-1 With Jitter Attenuator
Manufacturer
Teridian Semiconductor Corporation
Datasheet
REGISTER DESCRIPTION
ADDRESS N-1: STATUS MONITOR REGISTER
Page 11 of 37
BIT
6:4
7
3
2
1
0
NAME
TXNW
RSVD
RSVD
SGLO
FERR
LOS
TYPE
R/O
R/O
R/O
R/O
R/O
R/O
VALUE
DFLT
X
X
X
X
X
X
(continued)
2005 Teridian Semiconductor Corporation
Jitter Attenuator FIFO Error Flag:
This bit is set whenever a FIFO overflow or underflow occurred. It is
reset after a read operation to this register.
Reserved
Loss-of-Signal Indication:
NOTE: RPOSx and RNEGx are forced low when LOS=’1’. RCLK will
continue to output a line rate clock
Transmitter Not-Working Indication:
Reserved
Signal Low Indication:
0 : Proper Operation
1 : FIFO Overflow/Underflow
0 : Signal Detector detecting a valid receive input signal
1 : Standards-based Loss-of-Signal indication
0 : Transmitter OK
1 : Transmitter not working
0 : Receive signal level OK
1 : Receive signal level too low / Loss of signal
DESCRIPTION
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
78P2343JAT
Rev 2.2

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