sc16c650a NXP Semiconductors, sc16c650a Datasheet
sc16c650a
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sc16c650a Summary of contents
Page 1
... System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C650A operates 3.3 V and 2.5 V, and the industrial temperature range, and is available in plastic DIP40, PLCC44, and LQFP48 packages. 2. Features ...
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... Even-, Odd-, or No-Parity formats 1 1 2-stop bit 2 Baud generation ( Mbit/s) Loop-back controls for communications link fault isolation 10 +85 C. amb Rev. 04 — 20 June 2003 SC16C650A Version SOT187-2 7 1.4 mm SOT313-2 SOT129-1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... RECEIVE FIFO SHIFT REGISTERS REGISTER FLOW CONTROL LOGIC CONTROL CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RCLK BAUDOUT Rev. 04 — 20 June 2003 SC16C650A TX IR ENCODER RX IR DECODER DTR RTS OUT1, OUT2 MODEM LOGIC CTS RI DCD DSR 002aaa295 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... UART with 32-byte FIFO and IrDA encoder/decoder RCLK SC16C650AIA44 CS0 14 CS1 15 16 CS2 BAUDOUT 17 Rev. 04 — 20 June 2003 SC16C650A 39 RESET 38 OUT1 37 DTR 36 RTS 35 OUT2 INT 32 RXRDY 002aaa296 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... UART with 32-byte FIFO and IrDA encoder/decoder RCLK SC16C650AIB48 CS0 9 CS1 10 11 CS2 BAUDOUT 12 Rev. 04 — 20 June 2003 SC16C650A RESET 34 OUT1 33 DTR 32 RTS 31 OUT2 30 INT 29 RXRDY 002aaa298 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Baud out. BAUDOUT clock signal for the transmitter section of the UART. The clock rate is established by the reference oscillator frequency divided by a divisor specified in the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK. Rev. 04 — 20 June 2003 SC16C650A ...
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... Master Reset, during loop mode operations clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. I Receiver clock. RCLK is the 16 baud rate clock for the receiver section of the UART. Rev. 04 — 20 June 2003 SC16C650A © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Mode 1 supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. Power 2 supply voltage. Power Ground voltage. Rev. 04 — 20 June 2003 SC16C650A © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C650A is capable of operation Mbits/s with a 48 MHz external clock input (at 5 V). The rich feature set of the SC16C650A is available through internal registers. ...
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... The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the transmit trigger level. The SC16C650A provides independent trigger levels for both receiver and transmitter. To remain compatible with SC16C550, the transmit interrupt trigger level is set to 16 following a reset ...
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... EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C650A will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent ...
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... The interrupts are enabled by IER[5-7]. Care must be taken when handling these interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C650A will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority ...
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... Fig 5. Crystal oscillator connection. The generator divides the input 16 clock by any divisor from SC16C650A divides the basic crystal or external clock by 16. The frequency of the BAUDOUT output pin is exactly 16 (16 times) of the selected baud rate (BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator ...
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... DIVIDE-BY-1 LOGIC CLOCK OSCILLATOR LOGIC DIVIDE-BY-4 LOGIC Rev. 04 — 20 June 2003 SC16C650A Divisor for Baud rate 16 clock error 3840 2560 1745 0.026 1428 0.034 1280 640 320 160 107 0.312 0.628 40 27 1.23 20 ...
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... RX, RI, CTS, DSR, DCD transmit data is provided by the user. If the sleep mode is enabled and the SC16C650A is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user ...
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... REGISTER REGISTERS FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RCLK BAUDOUT Rev. 04 — 20 June 2003 SC16C650A TX IR ENCODER RX IR DECODER RTS DSR DTR CTS OUT1 RI OUT2 DCD 002aaa303 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder details the assigned bit functions for the fifteen SC16C650A internal registers. Bit 7 Bit 6 Bit 5 Bit 4 bit 7 ...
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... FIFO full; logic least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C650A and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... FIFO reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C650A in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • ...
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... Receive operation in mode ‘0’: When the SC16C650A is in 16C450 mode the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0 ...
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... FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C650A is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached. ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C650A provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Logic 0 or cleared = default condition. LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Logic 0 or cleared = default condition. Rev. 04 — 20 June 2003 SC16C650A Table 16). Table 17). Table 18). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode, the infrared TX output will be a logic 0 during idle data conditions. Rev. 04 — 20 June 2003 SC16C650A Section 6.7 generator”). © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and RI are disconnected from the SC16C650A I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C650A and the CPU. Table 20: Bit 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Line Status Register bits description ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C650A has changed from a logic logic 1. A modem Status Interrupt will be generated. Rev. 04 — 20 June 2003 SC16C650A …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... A modem Status Interrupt will be generated. [1] MSR[0] CTS Logic CTS change (normal default condition). Logic 1 = The CTS input to the SC16C650A has changed state since the last time it was read. A modem Status Interrupt will be generated. Enhanced Feature Register bits description Symbol Description EFR[7] Automatic CTS fl ...
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... EFR[5] Special Character Detect. Logic 0 = Special character detect disabled (normal default condition). Logic 1 = Special character detect enabled. The SC16C650A compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
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... Philips Semiconductors 7.11 SC16C650A external reset conditions Table 24: Register IER ISR LCR MCR LSR MSR FCR EFR Table 25: Output TX RTS DTR RXRDY TXRDY INT 8. Limiting values Table 26: In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg ...
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... OL (other outputs (databus (other outputs 800 A 1.85 OH (databus 400 A 1.85 OH (other outputs MHz - - [2] 500 for a listing of pins having internal pull-up resistors. Rev. 04 — 20 June 2003 SC16C650A 3.3 V 5.0 V Max Min Max Min Max 0.45 0.3 0.6 0.5 0.6 V 2 0.65 0.3 0.8 0.5 0.8 - 2 ...
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... Rev. 04 — 20 June 2003 SC16C650A 3.3 V 5.0 V Unit Max Min Max - MHz - ...
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... Conditions Min - 100 VALID ADDRESS t 6h VALID ACTIVE t 11d t 11d ACTIVE t t 12d 12h DATA Rev. 04 — 20 June 2003 SC16C650A 2.5 V 3.3 V 5.0 V Max Min Max Min Max clock cycle. 1 002aaa331 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... ACTIVE t t 16s 16h DATA VALID ACTIVE ACTIVE t 12h t 12d DATA Rev. 04 — 20 June 2003 SC16C650A 002aaa332 VALID ADDRESS ACTIVE t t 12d 12h 002aaa333 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... ACTIVE t t 13w 15d ACTIVE t 16h t 16s DATA t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE ACTIVE Rev. 04 — 20 June 2003 SC16C650A VALID ADDRESS t 7h ACTIVE t 13w t t 16s 16h 002aaa334 CHANGE OF STATE t 18d ACTIVE ACTIVE t 19d ACTIVE ACTIVE t 18d ...
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... UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C650A 002aaa112 NEXT DATA PARITY STOP START BIT BIT BIT 20d ACTIVE t 21d ...
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... Product data UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5– DATA BITS (5– Rev. 04 — 20 June 2003 SC16C650A NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY t 26d ...
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... DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C650A NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Philips Semiconductors Fig 18. Transmit ready timing in non-FIFO mode. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Rev. 04 — 20 June 2003 SC16C650A © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 04 — 20 June 2003 SC16C650A PARITY STOP BIT BIT D6 D7 002aaa346 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... UART with 32-byte FIFO and IrDA encoder/decoder UART FRAME DATA BITS BIT TIME RX BIT TIME Rev. 04 — 20 June 2003 SC16C650A 1/2 BIT TIME 3/16 BIT TIME 002aaa212 0-1 16X CLOCK DELAY DATA BITS UART FRAME 002aaa213 © ...
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... 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.656 0.656 0.63 0.63 0.695 0.695 0.048 0.05 0.650 0.650 0.59 0.59 0.685 0.685 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 20 June 2003 SC16C650A SOT187 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1. ...
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... 2 scale (1) ( 0.18 7.1 7.1 9.15 9.15 0.5 1 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 20 June 2003 SC16C650A SOT313 detail X (1) ( 0.75 0.95 0.95 7 0.2 0.12 0.1 o 0.45 0.55 0.55 0 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © ...
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... 0.53 0.36 52.5 14.1 2.54 0.38 0.23 51.5 13.7 0.021 0.014 2.067 0.56 0.1 0.015 0.009 2.028 0.54 REFERENCES JEDEC JEITA MO-015 SC-511-40 Rev. 04 — 20 June 2003 SC16C650A SOT129 3.60 15.80 17.42 15.24 0.254 3.05 15.24 15.90 0.14 0.62 0.69 0.6 0.01 0.12 0.60 0.63 EUROPEAN ISSUE DATE PROJECTION ...
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... C (SnPb process) or below 245 C (Pb-free process) – for all the BGA and SSOP-T packages 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Rev. 04 — 20 June 2003 SC16C650A ). stg(max) © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder 2 called small/thin packages. Rev. 04 — 20 June 2003 SC16C650A 3 350 mm so called © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS [6] PLCC , SO, SOJ suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, not recommended VSSOP Rev. 04 — 20 June 2003 SC16C650A [2] Reflow Dipping [3] suitable suitable [5] suitable suitable [6][7] suitable [8] suitable 10 C measured in the atmosphere of the reflow © ...
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... Product data (9397 750 09832). ECN 853-2378 28891 of 10 September 2002. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder 13: Capacitors’ values changed and Rev. 04 — 20 June 2003 SC16C650A © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Rev. 04 — 20 June 2003 SC16C650A Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C650A external reset conditions . . . . . . 30 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...