sc16c750-04 NXP Semiconductors, sc16c750-04 Datasheet - Page 31
sc16c750-04
Manufacturer Part Number
sc16c750-04
Description
Sc16c750 Universal Asynchronous Receiver/transmitter Uart With 64-byte Fifo
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C750-04.pdf
(45 pages)
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Philips Semiconductors
Table 26:
T
[1]
[2]
[3]
[4]
9397 750 11623
Product data
Symbol
t
t
N
28d
RESET
amb
Fig 6. General read timing when using AS signal.
Applies to external clock, crystal oscillator max 24 MHz.
Applicable only when AS is tied LOW.
= 333 ns (for Baudrate
= 1 s (for Baudrate
= 4 s (for Baudrate
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x
IOWstrobe
= 40 C to +85 C; V
CS1–CS0
IOR, IOR
D0–D7
A0–A2
DDIS
CS2
AC electrical characteristics
AS
Parameter
delay from start to reset TXRDY
Reset pulse width
baud rate divisor
max
=
10.1 Timing diagrams
------------------------------------- -
2 Baudrate
max
max
max
= 460.8 kbits/s)
= 115.2 kbits/s)
CC
t
8d
= 1.5 Mbits/s)
t
4w
1
t
5s
= 2.5 V, 3.3 V or 5 V 10%, unless otherwise specified.
t
6s
t
max
7d
t
11d
ADDRESS
VALID
t
12d
…continued
ACTIVE
VALID
t
7w
ACTIVE
t
t
5h
6h
Rev. 04 — 20 June 2003
Conditions
DATA
t
12h
t
7h
t
11d
t
9d
Min
-
100
1
2.5 V
Max
8
-
2
16
1 1
Min
-
40
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
3.3 V
Max
8
-
2
1
16
UART with 64-byte FIFO
clock cycle.
1 1
SC16C750
Min
-
40
5.0 V
002aaa331
Max
8
-
2
16
1 R
31 of 45
Unit
R
ns
clk
clk
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