sc16c751b NXP Semiconductors, sc16c751b Datasheet
sc16c751b
Related parts for sc16c751b
sc16c751b Summary of contents
Page 1
... System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics. The SC16C751B operates 3.3 V and 2.5 V, the industrial temperature range and is available in the plastic HVQFN24 package. 2. Features ...
Page 2
... +85 C. amb Description plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs © NXP B.V. 2008. All rights reserved. Version SOT616 ...
Page 3
... Fig 1. 5. Pinning information 5.1 Pinning Fig 2. SC16C751B_2 Product data sheet SC16C751B DATA BUS AND CONTROL LOGIC REGISTER SELECT LOGIC INTERRUPT CONTROL LOGIC Block diagram of SC16C751B terminal 1 index area SC16C751BIBS Transparent top view Pin configuration for HVQFN24 Rev. 02 — ...
Page 4
... TX is set to the marking (HIGH) level as a result of Master Reset. 19 power 2 supply voltage. 10 power Ground voltage. Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs for register addresses. © NXP B.V. 2008. All rights reserved ...
Page 5
... The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C751B is capable of operation Mbit/s with an 80 MHz external clock input (at 5 V). The rich feature set of the SC16C751B is available through internal registers. Automatic hardware fl ...
Page 6
... MSB of Divisor Latch Flow control mechanism INT pin activation Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs WRITE mode [1] Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register n/a n/a Scratchpad Register ...
Page 7
... Automatic hardware flow control is selected by setting MCR[5] (RTS) and MCR[1] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, the SC16C751B will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent ...
Page 8
... Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs XTAL1 XTAL2 1 1.8432 MHz 002aaa870 16 Table 5 Equation Using 3.072 MHz crystal Desired Divisor for baud rate ...
Page 9
... Sleep mode automatically after the last character is transmitted or read by the user. In any case, the Sleep mode will not be entered while an interrupt(s) is pending. The SC16C751B will stay in the Sleep mode of operation until it is disabled by setting IER[ logic 0. ...
Page 10
... REGISTERS REGISTER FLOW CONTROL LOGIC RECEIVE RECEIVE FIFO SHIFT REGISTERS REGISTER FLOW CONTROL LOGIC MODEM CONTROL CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 02 — 10 October 2008 SC16C751B TX MCR[ RTS CTS LOGIC 002aad012 © NXP B.V. 2008. All rights reserved ...
Page 11
... Do not write a logic 1 to the reserved bits. Read of the reserved bits reflect unknown values. [4] The ‘Special register set’ is accessible only when LCR[7] is set to a logic 1. SC16C751B_2 Product data sheet details the assigned bit functions for the fifteen SC16C751B internal registers. The [1] Bit 7 Bit 6 Bit 5 ...
Page 12
... FIFO full; logic least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C751B and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
Page 13
... FIFO reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C751B in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • ...
Page 14
... FIFO RCVR trigger levels FCR[6] RX FIFO trigger level (bytes) 16-byte operation Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs 9. 64-byte operation © NXP B.V. 2008. All rights reserved ...
Page 15
... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C751B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
Page 16
... LCR[1:0] Word length bit 1, bit 0. These two bits specify the word length to be transmitted or received (see logic 0 or cleared = default condition Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Table 13). Table 14). Table 15). © ...
Page 17
... Word length (bits) Stop bit length (bit times LCR[1:0] word length LCR[0] Word length (bits Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs © NXP B.V. 2008. All rights reserved ...
Page 18
... Loopback. Enable the local Loopback mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS are disconnected from the SC16C751B I/O pins. Internally the modem data and control pins are connected into a loopback data configuration (see mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
Page 19
... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C751B and the CPU. Table 18. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C751B_2 Product data sheet Line Status Register bits description Description FIFO data error. ...
Page 20
... MSR[3:1] reserved [1] MSR[0] CTS logic CTS change (normal default condition) logic 1 = the CTS input to the SC16C751B has changed state since the last time it was read. A modem Status Interrupt will be generated. Reset state for registers Reset state IER[7: ISR[7: ISR[ LCR[7: MCR[7: LSR[ ...
Page 21
... (other outputs 1.85 OH (data bus 1.85 OH (other outputs 800 A 1.85 OH (data bus 400 A 1.85 OH (other outputs) [2] 500 Rev. 02 — 10 October 2008 SC16C751B Min Max - 0.3 5 +85 65 +150 - 500 = 2 3 Max Min ...
Page 22
... Figure 7 [ load; - 100 Figure 9 - 100 [2] 8T 24T RCLK - 100 [3] 100 Rev. 02 — 10 October 2008 SC16C751B Min Max Min - ...
Page 23
... Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs valid address 6s' 7h' 7w active t t 12d 12h 002aad015 valid address t t 7h' 6s' active ...
Page 24
... Product data sheet 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs t 17d change of state change of state t 18d active active Rev. 02 — 10 October 2008 SC16C751B change of state t 18d active active t 19d active active 002aad013 002aaa112 © NXP B.V. 2008. All rights reserved ...
Page 25
... data bits 6 data bits 7 data bits active transmitter ready t 22d t 23d 16 baud rate clock Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs next data parity stop start bit bit bit 20d active t ...
Page 26
... 2.5 scale (1) ( 4.1 2.75 4.1 2.75 0.5 2.5 3.9 2.45 3.9 2.45 REFERENCES JEDEC JEITA MO-220 - - - Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION SOT616 ISSUE DATE ...
Page 27
... Solder bath specifications, including temperature and impurities SC16C751B_2 Product data sheet 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 02 — 10 October 2008 SC16C751B © NXP B.V. 2008. All rights reserved ...
Page 28
... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 12. Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Figure 12) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
Page 29
... Divisor Latch MSB First In, First Out Least Significant Bit Most Significant Bit Transistor-Transistor Logic Universal Asynchronous Receiver and Transmitter Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs peak temperature © NXP B.V. 2008. All rights reserved. time 001aac844 ...
Page 30
... pins” and “at input only pins” n Product data sheet Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Change notice Supersedes - SC16C751B_1 Footnote 1 on page 1 st paragraph: removed phrase “and select the DMA - - © NXP B.V. 2008. All rights reserved ...
Page 31
... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 10 October 2008 SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs © NXP B.V. 2008. All rights reserved ...
Page 32
... Interrupt Status Register (ISR 7.5 Line Control Register (LCR 7.6 Modem Control Register (MCR 7.7 Line Status Register (LSR 7.8 Modem Status Register (MSR 7.9 Scratchpad Register (SPR 7.10 SC16C751B external reset conditions . . . . . . 20 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 22 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 23 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 12 Soldering of SMD packages ...