sc16c554dbib64 NXP Semiconductors, sc16c554dbib64 Datasheet - Page 31

• Manufacturer Part Number: sc16c554dbib64
• Description: 5 V, 3.3 V And 2.5 V Quad Uart, 5 Mbit/s Max. With 16-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SC16C554B_554DB_3
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 12:
The SC16C554B/554DB provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the Interrupt Status Register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits.
four prioritized interrupt levels and the interrupt sources associated with each of these
interrupt levels.
Table 13:
Table 14:
FCR[7]
0
0
1
1
Priority
level
1
2
2
3
4
Bit
7:6
5:4
3:1
0
RCVR trigger levels
Interrupt source
Interrupt Status Register bits description
ISR[5]
0
0
0
0
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
FCR[6]
0
1
0
1
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
ISR[4]
0
0
0
0
0
Table 13 “Interrupt source”
Rev. 03 — 1 September 2005
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
Reserved; set to 0.
INT priority bits 2 to 0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used
as a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
ISR[3]
0
0
1
0
0
RX FIFO trigger level
1
4
8
14
ISR[2]
1
1
1
0
0
ISR[1]
1
0
0
1
0
shows the data values (bits 0 to 5) for the
SC16C554B/554DB
ISR[0]
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Receive Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status
Register)
Table
13).
31 of 56