sc16c850lib NXP Semiconductors, sc16c850lib Datasheet - Page 6

• Manufacturer Part Number: sc16c850lib
• Description: Sc16c850l 1.8 V Single Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
SC16C850L_4
Product data sheet
Symbol
16/68
A0
A1
A2
CD
CS
CTS
DSR
DTR
Fig 5. Pin configuration for HVQFN32
a. 16 mode
index area
terminal 1
Pin description
Pin
TFBGA36 HVQFN32
-
C1
C3
B1
E3
B6
D3
F2
E1
RX
CS
D4
D5
D6
D7
TX
16
1
2
3
4
5
6
7
8
5.2 Pin description
Transparent top view
SC16C850LIBS
2
19
18
17
26
8
24
25
22
(16 mode)
Type
I
I
I
I
I
I
I
I
O
24
23
22
21
20
19
18
17
Description
Bus select. Intel or Motorola bus select.
When 16/68 pin is at logic 1 or left unconnected (internally pulled-up) the
device will operate in Intel bus (16 mode) type of interface.
When 16/68 pin is at logic 0, the device will operate in Motorola bus (68 mode)
type of interface.
Address 0 select bit. Internal register address selection.
Address 1 select bit. Internal register address selection.
Address 2 select bit. Internal register address selection.
Carrier Detect (active LOW). A logic 0 on this pin indicates that a carrier has
been detected by the modem. Status can be tested by reading MSR[7].
Chip Select (active LOW). In 16 mode or 68 mode, this input is chip select for
the UART.
Clear to Send (active LOW). A logic 0 on the CTS pin indicates the modem
or data set is ready to accept transmit data from the SC16C850L. Status can
be tested by reading MSR[4].
Data Set Ready (active LOW). A logic 0 on this pin indicates the modem or
data set is powered-on and is ready for data exchange with the UART. Status
can be tested by reading MSR[5].
Data Terminal Ready (active LOW). A logic 0 on this pin indicates that the
SC16C850L is powered-on and ready. This pin can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set the DTR output to
logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset.
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
002aac419
Rev. 04 — 13 December 2007
CTS
RESET
DTR
RTS
INT
A0
A1
A2
b. 68 mode
index area
terminal 1
RX
CS
D4
D5
D6
D7
TX
68
1
2
3
4
5
6
7
8
Transparent top view
SC16C850LIBS
(68 mode)
SC16C850L
© NXP B.V. 2007. All rights reserved.
24
23
22
21
20
19
18
17
002aac631
CTS
RESET
DTR
RTS
IRQ
A0
A1
A2
6 of 54