sc16c2550-03 NXP Semiconductors, sc16c2550-03 Datasheet - Page 26

• Manufacturer Part Number: sc16c2550-03
• Description: Sc16c2550 Dual Uart With 16 Bytes Of Transmit And Receive Fifos And Infrared Irda Encoder/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11621
Product data
7.8 Modem Status Register (MSR)
Table 18:
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C2550 is connected. Four bits
of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 19:
Bit
1
0
Bit
7
6
5
4
3
2
Line Status Register bits description
Modem Status Register bits description
Symbol
LSR[1]
LSR[0]
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Rev. 03 — 19 June 2003
Description
Overrun error.
Receive data ready.
Description
CD. During normal operation, this bit is the complement of the CD
input. Reading this bit in the loop-back mode produces the state of
MCR[3] (OP2).
RI. During normal operation, this bit is the complement of the RI
input. Reading this bit in the loop-back mode produces the state of
MCR[2] (OP1).
DSR. During normal operation, this bit is the complement of the
DSR input. During the loop-back mode, this bit is equivalent to
MCR[0] (DTR).
CTS. During normal operation, this bit is the complement of the
CTS input. During the loop-back mode, this bit is equivalent to
MCR[1] (RTS).
CD
RI
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the
receive shift register. This happens when additional data arrives
while the FIFO is full. In this case, the previous data in the shift
register is overwritten. Note that under this condition, the data
byte in the receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the error.
Logic 0 = No data in receive holding register or FIFO (normal
default condition).
Logic 1 = Data has been received and is saved in the receive
holding register or FIFO.
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C2550 has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
[1]
[1]
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2550
encoder/decoder
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