sc16is850l NXP Semiconductors, sc16is850l Datasheet - Page 23

• Manufacturer Part Number: sc16is850l
• Description: Single Uart With I2c-bus/spi Interface, 128 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16IS850L
Product data sheet
8.3.1 FIFO mode
8.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO
trigger levels.
Table 8.
[1]
[2]
Table 9.
[1]
Bit
3
2
1
0
FCR[7]
0
0
1
1
7:6
5:4
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
FCR[7:6] Receive trigger level in 32-byte FIFO mode
FCR[5:4] Transmit trigger level in 32-byte FIFO mode
FCR[3]
FCR[2]
FCR[1]
FCR[0]
Symbol
FIFO Control Register bits description
RCVR trigger levels
FCR[6]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
These bits are used to set the trigger levels for receive FIFO interrupt and flow
control. The SC16IS850L will issue a receive ready interrupt when the number
of characters in the receive FIFO reaches the selected trigger level. Refer to
Table
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16IS850L will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table
reserved
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
9.
10.
Rev. 1 — 22 July 2011
RX FIFO trigger level (bytes) in 32-byte FIFO mode
8
16
24
28
Section
Section
8.16,
8.15,
Section
Section
Single UART with I
8.17,
8.17,
Section
Section
[1]
[2]
.
.
8.18.
8.18.
Section 7.3 “FIFO
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
operation”).
[1]
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